VHDL events

Discussion in 'VHDL' started by no.spam.mole@googlemail.com, Dec 9, 2008.

  1. Guest

    Hi,

    I have just started trying to learn VHDL and I am wondering about the
    "event" keyword. If I write:

    process(clock)
    begin
    if clock'event and clock = '1' then

    end if
    end process;

    then I step inside the if statement every rising clock edge. If I do
    the opposite:

    process(clock)
    begin
    if clock'event and clock = '0' then

    end if
    end process;

    then do I step inside every falling clock edge? Also, can I do this:

    process(clock)
    begin
    if clock'event and clock = '0' then

    elsif clock'event and clock = '1' then

    end if
    end process;

    to do something on the falling and rising clock edges? I remember
    seeing a post which said this was bad, but I don't remember why.

    Thanks,
    David
    , Dec 9, 2008
    #1
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  2. Tricky Guest

    On 9 Dec, 09:35, wrote:
    > Hi,
    >
    > I have just started trying to learn VHDL and I am wondering about the
    > "event" keyword.  If I write:
    >
    > process(clock)
    > begin
    >    if clock'event and clock = '1' then
    >
    >   end if
    > end process;
    >
    > then I step inside the if statement every rising clock edge.  If I do
    > the opposite:
    >
    > process(clock)
    > begin
    >    if clock'event and clock = '0' then
    >
    >   end if
    > end process;
    >
    > then do I step inside every falling clock edge?  Also, can I do this:
    >
    > process(clock)
    > begin
    >    if clock'event and clock = '0' then
    >
    >    elsif clock'event and clock = '1' then
    >
    >   end if
    > end process;
    >
    > to do something on the falling and rising clock edges?  I remember
    > seeing a post which said this was bad, but I don't remember why.
    >
    > Thanks,
    > David


    It depends on the architecture you are using. FPGA's wont accept both
    edges (I dont know anything about ASICs).

    It is perfectly acceptable VHDL, and will simulate as you expect. Just
    dont expect it to work in real hardware. Use one edge or the other,
    and if you need both edges then just multiply your clock x2

    Coincidently, VHDL has 2 functions that are a bit more explicit:
    rising_edge(clk) and falling_edge(clk) which you can use in place of
    clk'event and clk = '1'/'0';

    The problem with clk'event and clk = '1' is that it will be true when
    the clock changes from ANYTHING to a '1'
    Rising/falling_edge functions are only true when the clk changes from
    '0' to '1'.
    These functions werent standard until 1993, and so alot of older
    examples will use the 'event method.
    Tricky, Dec 9, 2008
    #2
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  3. > "Tricky" <> wrote in message
    > news:...
    > On 9 Dec, 09:35, wrote:
    > Rising/falling_edge functions are only true when the clk changes from
    > '0' to '1'.


    Actually, rising_edge() and falling_edge() are more flexible than you
    suggest. They will detect changes from anything that is interpreted as low
    to anything that is interpreted as high, or vice-versa, meaning that
    simulation will match synthesis correctly.

    For example, on a wire-ORed clock signal, rising_edge() would correctly
    detect a transition from '0' to 'H' whereas the traditional form using
    'event wouldn't. Conversely, for example, rising_edge() will correctly not
    detect a transition from 'H' to '1' as a valid clock whereas 'event would.
    David Spencer, Dec 9, 2008
    #3
  4. Andy Guest

    On Dec 9, 5:04 am, Tricky <> wrote:
    > It depends on the architecture you are using. FPGA's wont accept both
    > edges (I dont know anything about ASICs).
    >
    > It is perfectly acceptable VHDL, and will simulate as you expect. Just
    > dont expect it to work in real hardware. Use one edge or the other,
    > and if you need both edges then just multiply your clock x2


    Some synthesis tools will not accept a single process with two edge
    detections. Others will, but will not accept assignments to the same
    variable or signal on both edges (since that would require a DDR
    register).

    Perhaps they should, since DDR behavior can be implemented with two
    SDR registers and 3 xor (or xnor) gates:

    process (clk) is
    variable qr, qf : std_logic;
    begin
    if rising_edge(clk) then
    qr := d xor qf; -- registered encode of input
    elsif falling_edge(clk) then
    qf := d xor qr; -- registered encode of input
    end if;
    q <= qr xor qf; -- combinatorial decode of output
    end process;

    This can also be re-written using signals and three processes if
    you're synthesis tool does not like a single process for all three
    (two clock edges and the combinatorial decode). Note that it does not
    necessarily have to be opposite edges of one clock signal. You could
    make it work off any two clocks as long as they are locked
    synchronously to each other.

    For small circuits that need DDR behavior, this is often more
    efficient than using a DLL/PLL to double the clock.

    Andy
    Andy, Dec 9, 2008
    #4
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