VHDL Loops Execution

Discussion in 'VHDL' started by dionysian83@gmail.com, Sep 2, 2008.

  1. Guest

    I am learning VHDL and one thing i still dont get is how loops are
    executed in the vhdl. For, example i have code that will write to a
    file for debugging perposes and it is implemented using a while loop:
    while word_write_count < 32 loop

    write ( trace_line,string'("Address: "));
    write ( trace_line,word_write_count);
    write ( trace_line,string'(" "));
    write
    ( trace_line,To_bitvector(frame_information(word_write_count)));
    writeline (load_file,trace_line);

    word_write_count := word_write_count + 1;

    end loop;
    But i still dont get in what sequence this code will execute. Will it
    execute top to bottom? If so will changes made in the above line be
    accessible to lines below it? how long will it take the code to
    execute? Its obviously not synched with the systems clock so how would
    i know when it has completed. Can some one help me understand how
    loops are implemented behind the scenes in VHDL?

    Thank you.
    , Sep 2, 2008
    #1
    1. Advertising

  2. Guest

    On Sep 2, 6:24 pm, wrote:
    > I am learning VHDL and one thing i still dont get is how loops are
    > executed in the vhdl. For, example i have code that will write to a
    > file for debugging perposes and it is implemented using a while loop:
    > while word_write_count < 32 loop
    >
    >                                         write ( trace_line,string'("Address: "));
    >                                         write ( trace_line,word_write_count);
    >                                         write ( trace_line,string'(" "));
    >                                         write
    > ( trace_line,To_bitvector(frame_information(word_write_count)));
    >                                         writeline (load_file,trace_line);
    >
    >                                         word_write_count := word_write_count + 1;
    >
    >                                 end loop;
    > But i still dont get in what sequence this code will execute. Will it
    > execute top to bottom? If so will changes made in the above line be
    > accessible to lines below it? how long will it take the code to
    > execute? Its obviously not synched with the systems clock so how would
    > i know when it has completed. Can some one help me understand how
    > loops are implemented behind the scenes in VHDL?
    >
    > Thank you.


    Your 'while' statement is what's called a sequential statement, and
    the code appears to reference only variables and function calls.
    Therefore, the code as you wrote it, can be read in pretty much the
    same way you'd read the equivalent piece of code in C, Pascal, or any
    other vanilla programming language. Either of the complementary
    constructs (concurrent statements, or signals) leads you into the
    world of time, clocks, events, synchronization, and process semantics.
    But you're not there yet.

    So yes, it will run from top to bottom, the effect of executing each
    line will be visible to the next line, and it completes
    instantaneously. That means zero time only as far as the simulated
    circuit goes; of course it will use real CPU time :) It will be
    completed when the loop condition becomes false and the line below the
    loop starts to execute.

    - Kenn
    , Sep 3, 2008
    #2
    1. Advertising

  3. Tricky Guest

    On 2 Sep, 23:24, wrote:
    > I am learning VHDL and one thing i still dont get is how loops are
    > executed in the vhdl. For, example i have code that will write to a
    > file for debugging perposes and it is implemented using a while loop:
    > while word_write_count < 32 loop
    >
    >                                         write ( trace_line,string'("Address: "));
    >                                         write ( trace_line,word_write_count);
    >                                         write ( trace_line,string'(" "));
    >                                         write
    > ( trace_line,To_bitvector(frame_information(word_write_count)));
    >                                         writeline (load_file,trace_line);
    >
    >                                         word_write_count := word_write_count + 1;
    >
    >                                 end loop;
    > But i still dont get in what sequence this code will execute. Will it
    > execute top to bottom? If so will changes made in the above line be
    > accessible to lines below it? how long will it take the code to
    > execute? Its obviously not synched with the systems clock so how would
    > i know when it has completed. Can some one help me understand how
    > loops are implemented behind the scenes in VHDL?
    >
    > Thank you.


    As you have no wait statements inside the loop, it will execute and
    write 32 lines to a file, each line containing the same results as
    each other as it will all take place in the single delta cycle. You
    need wait statements inside the loop. What are you trying to capture?
    Tricky, Sep 3, 2008
    #3
  4. Guest

    On Sep 3, 3:53 am, Tricky <> wrote:
    > As you have no wait statements inside the loop, it will execute and
    > write 32 lines to a file, each line containing the same results as
    > each other as it will all take place in the single delta cycle.


    The OP used variable assignment (the ':=' ) which means that each line
    will be *different*, because variable updates take effect immediately.
    The outputs would only be the same if the thing being printed was a
    *signal*.

    Ask Modelsim about this:

    use std.textio.all;
    entity e is begin
    end entity e;

    architecture a of e is
    begin
    process
    variable v :integer := 1;
    variable oline : line;
    begin
    while v < 10 loop
    write(oline, v);
    writeline(output,oline);
    v := v+1;
    end loop;
    wait; -- all done
    end process;
    end architecture a;

    And it will tell you:

    # Loading work.e(a)
    run
    # 1
    # 2
    # 3
    # 4
    # 5
    # 6
    # 7
    # 8
    # 9

    HTH,

    - Kenn
    , Sep 3, 2008
    #4
  5. Andy Guest

    On Sep 3, 2:53 am, Tricky <> wrote:
    >
    > As you have no wait statements inside the loop, it will execute and
    > write 32 lines to a file, each line containing the same results as
    > each other as it will all take place in the single delta cycle. You
    > need wait statements inside the loop. What are you trying to capture?


    That is false. The loop should write a different element from the
    array on each line. All lines will be written at the same simulation
    time tick, but that is probably what was intended anyway. The variable
    write_word_count updates immediately after it is assigned, and does
    not need a wait statement or other process suspension to update like a
    signal does.

    That said, it is generally not recommended to control a while-loop
    with an incrementing index. That's what for-loops are for. Using the
    appropriate type of loop tells the reader/reviewer/maintainer of your
    code right up front what your loop does. But your code should work
    just fine. Did you remember to set word_count to zero before entering
    the loop? Here again, a for-loop does that for you (initialize, test
    and loop in one statement).

    The answer to the original question is that yes, statements in
    sequential loop statements (excluding generate-loops) execute in
    order, just like any sequential statements anywhere in a process or
    subprogram. What does not happen in order is signal updating. Signals
    do not update until the process suspends, waiting for another clock or
    input to change. They do not wait to update until the clock or input
    changes, just until the process suspends to wait for the input(s).
    Variables, however, update immediately upon execution of the
    assignment statement.

    Andy
    Andy, Sep 3, 2008
    #5
  6. Tricky Guest

    On 3 Sep, 14:05, Andy <> wrote:
    > On Sep 3, 2:53 am, Tricky <> wrote:
    >
    >
    >
    > > As you have no wait statements inside the loop, it will execute and
    > > write 32 lines to a file, each line containing the same results as
    > > each other as it will all take place in the single delta cycle. You
    > > need wait statements inside the loop. What are you trying to capture?

    >
    > That is false.  The loop should write a different element from the
    > array on each line. All lines will be written at the same simulation
    > time tick, but that is probably what was intended anyway. The variable
    > write_word_count updates immediately after it is assigned, and does
    > not need a wait statement or other process suspension to update like a
    > signal does.
    >
    > That said, it is generally not recommended to control a while-loop
    > with an incrementing index. That's what for-loops are for. Using the
    > appropriate type of loop tells the reader/reviewer/maintainer of your
    > code right up front what your loop does. But your code should work
    > just fine. Did you remember to set word_count to zero before entering
    > the loop? Here again, a for-loop does that for you (initialize, test
    > and loop in one statement).
    >
    > The answer to the original question is that yes, statements in
    > sequential loop statements (excluding generate-loops) execute in
    > order, just like any sequential statements anywhere in a process or
    > subprogram. What does not happen in order is signal updating. Signals
    > do not update until the process suspends, waiting for another clock or
    > input to change. They do not wait to update until the clock or input
    > changes, just until the process suspends to wait for the input(s).
    > Variables, however, update immediately upon execution of the
    > assignment statement.
    >
    > Andy


    Yup. My bad.

    Must pay more attention next time.
    Tricky, Sep 3, 2008
    #6
  7. mreister

    Joined:
    Aug 19, 2008
    Messages:
    10
    Thank you all very much for your replies. Yes, i was intending the statement to run sequentially just like in C. However, what i dont get is how is it physically implemented on the FPGA? If it is not synched with the system clock how can the variables be implemented with a flip flop?

    I was told that using the while loops like i did will in general not synthesis and that is ok because it is just debugging code.

    HTML:
    So yes, it will run from top to bottom, the effect of executing each
    line will be visible to the next line, and it completes
    instantaneously. That means zero time only as far as the simulated
    circuit goes; of course it will use real CPU time  It will be
    completed when the loop condition becomes false and the line below the
    loop starts to execute
    If it executes in CPU time i take it that the FPGA cannot synthesize the code i used. If i understand you correctly you are saying that the CPU simulating this code runs my code and not the FPGA. But what if i wanted to use varabiles in code that will synthesize? How would the variables used be updated instantly? Wont there be latches used instead of flip flops? Isn't this undesireable?
    mreister, Sep 3, 2008
    #7
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. afd
    Replies:
    1
    Views:
    8,293
    Colin Paul Gloster
    Mar 23, 2007
  2. Thunder

    Re: 'for' loops in VHDL

    Thunder, Jun 27, 2007, in forum: VHDL
    Replies:
    1
    Views:
    545
    Jonathan Bromley
    Jun 27, 2007
  3. Jonathan Bromley

    Re: 'for' loops in VHDL

    Jonathan Bromley, Jun 27, 2007, in forum: VHDL
    Replies:
    0
    Views:
    452
    Jonathan Bromley
    Jun 27, 2007
  4. Thunder

    'for' loops in VHDL

    Thunder, Jun 27, 2007, in forum: VHDL
    Replies:
    3
    Views:
    36,316
  5. Me
    Replies:
    2
    Views:
    237
Loading...

Share This Page