VHDL--usage of WAIT statement in PROCESS

Discussion in 'VHDL' started by anil, May 13, 2006.

  1. anil

    anil Guest

    Hello,

    iam confused with the flow of simulation when a WAIT statement
    is used in the middle of statements within a PROCESS.
    please ,help me out of this with some relevant description.
    anil, May 13, 2006
    #1
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  2. > iam confused with the flow of simulation when a WAIT statement
    > is used in the middle of statements within a PROCESS.
    > please ,help me out of this with some relevant description.


    In a simulation cycle, a fraction of the processes become active,
    either when there is an event on the sensitivity list (process has no
    wait statement) or when the condition in the current wait statement
    becomes true.

    Active processes with no sensitivity list will then run code from the
    current wait statement until the next wait statement is encountered:

    process
    begin
    -- statements1
    WAIT UNTIL CLK='1';
    -- statements2
    WAIT UNTIL CLK='1';
    -- statements3
    end;

    This process will execute statements1 on initialization. Then it
    becomes inactive until CLK becomes "1". Note that if CLK is already
    "1", it will wait until CLK has some other value and then CLK becomes
    "1".

    After CLK becomes "1", the processes will execute statements2 and then
    wait until CLK becomes "1" for a second time.

    After that, it will execute statements3 and loop back to statements1,
    waiting until CLK becomes "1" for a third time.

    --
    If you do not like the behaviour that the process waits if the CLK is
    already one, you must use IF statements, see the LRM

    http://www.microlab.ch/courses/vlsi/vhdl-ieee/TUTORIAL/IEEE/HTML/1076_8.HTM#8.1


    process
    begin
    -- statements1
    if CLK /='1' then
    wait until CLK='1'
    end if;

    Hubble.
    Reiner Huober, May 15, 2006
    #2
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  3. anil

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
    38
    'wait for' statement is useless when it comes to synthesize.you can actually use a mod-n counter for generating a delay.
    vhdlguru.blogspot.com/2010/03/synthesizable-delay-generator-instead.html
    vipinlal, Mar 4, 2010
    #3
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