VHDL Vector Assignment

[falcon734]

I'm trying to write VHDL structurals of some circuits. One really stupid problem I've come up against: some of the circuit vector outputs are declared such as wordline<1:63:2> and wordline<0:62:2>, which indicates assignment to the 32 odd and even bits of a 64 bit vector. I've been trying to figure out how to do that in VHDL without portmapping each individual bit, and I haven't found a good answer. Any advice?