xst:737

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hello, I'm using ise and i'm trying to gather 30 words of 8-bit in type array from external source and send every word to a diffrent 8-bit alias and all the time it bothers me with these warnings:

<Xst:737 - Found 1-bit latch for signal <Hex_data2_197>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 5-bit latch for signal <ZDA_count>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.>


I checked out what could be the reason for this problem- that i should consider all the options that might be and so i did - but as if nothing happened .. Here's my code :

if countp="001" and data_ready_uart ='1' then
if ZDA_count<31 then

m_ZDA(addr_ZDA)<=data_out_UART;
addr<=addr+1;
addr_ZDA<=addr_ZDA+1;
ZDA_count<=ZDA_count+1;
state<=ZDA;
else
state<=ZDA;
ZDA_count<=1;
addr_zda<=1;
P00<=m_ZDA(1);
P011<=m_ZDA(2);
|
|
--my array is 1 X 30

thank you
 
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Consider the first two tests:

if countp="001" and data_ready_uart ='1' then
if ZDA_count<31 then

If either of these tests are false, none of the signals get new values - this means, the old values have to be kept. This results in latches to be generated.
 
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Thank you, I think I got it but as you know in vhdl from one solved problem you get another one.. or three:

Xst:646 - Signal <M_ZDA> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Xst:737 - Found 3-bit latch for signal <countp>. Latches may be generated from incomplete case or if statements...=>so as for <addr_ZDA>,<ZDA_count>
and Xst:2677-Node <addr_ZDA_0> of sequential type is unconnected in block <Enabling_Data_on_LCD>.=>to all its bits and so as for <countp>, <ZDA_count>.

here's the new code:

process(data_press,data_ready_uart,data_out_uart)
begin
if data_press="1100" then
countp<=countp+1;
state<=idle;
elsif data_press="1111" then
state<=idle;
case state is
when idle=>
if countp="001" then
state<=ZDA;
else
ZDA_count<=1;
M_ZDA<=(others=>x"00");
addr_ZDA<=1;
P0<=BB;
|
| --nothing with the array here
end if;
when ZDA=>if countp="001" then
if data_ready_uart ='1' then
if ZDA_count<31 then
m_ZDA(addr_ZDA)<=data_out_UART;
addr_ZDA<=addr_ZDA+1;
ZDA_count<=ZDA_count+1;
state<=ZDA;
else
state<=ZDA;--line 29
ZDA_count<=31;
addr_zda<=1;
end if;
elsif ZDA_count=31 then
addr_zda<=1;
state<=ZDA;
ZDA_count<=1;
P00<=m_ZDA(1);
|
|
end if;

else
state<=idle;
countp<="000";
ZDA_count<=1;
addr_zda<=1;
end if;
when others=>
state<=idle;
M_ZDA<=(others=>x"00");
ZDA_count<=1;
addr_zda<=1;
P0<=BB;
|
end end end

now, first of all- I cant understand why it thinks that signal M_ZDA is not in use.
Second- if I understood correctly the main issue for the latch problem is that when an "if" is open with several implementations , the "else" should give an alternative to those specific imps and so I did (at least I think I did).
Third- maybe all the warnings is a result of the one or more missing signals that are being assumed (xst 819).
And forth- I need a little advice- I think there might be a collision between data_ready_uart (which is a real input) and the signal ZDA_count, that's why I assumed (line 29) when ZDA_count finish its counting and still data_ready_uart goes high, ZDA_count value must has a value of 31 and state should repeat it self. I'm afraid it would stuck there.

I hope I made my things clear, thank you very much.
 
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1. M_ZDA is only assigned, but nowhere in the process it's being read; This means, the assignments and the signal itself, can be discarded.
2. you have this statement
countp<=countp+1;
This means the previous value of countp is used, thus needing a latch (because this process isn't clocked)

You may have to rethink what you want to do here -- and whether you really don't want to use a clock signal (then you'll get the safer flipflops)
 
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1.What is the meaning of read than, if not this -" P00<=m_ZDA(1); " ?
can you give an example please?
2. So your'e saying it is better to use a clock so I can get safer flipflops and make latchs disappear?
 
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1. Uhmm... I think I had missed that assignment; You're right, that makes the signal read; then the warning seems a bit weird to me as well

2. Yeah the tool is warning as normally flipflops are preferred over latches.
In another thread on the forum the difference between flipflops was explained.
 

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