I read in\n[URL]http://rti.etf.bg.ac.rs/rti/ri5rvl/tutorial/TUTORIAL/IEEE/HTML/1076_12.HTM[/URL]\nthat signal is active during simulation cycle\n\n- If one of its sources is active or\n- the signal is named in the formal part of an association element in a\nport association list and the the corresponding actual is active.\n\n=1= This immediately raises the question: how is the activity status\npropagated? We see that the source or active port's actual causes formal\nto be active. I do not understand why activity propagates down the\nhierarchy: when you have active parent module signal then, connected as\ninput to the children, submodules will see it's activity as formal part\nactivity. Why activity should not propagate in the opposite direction,\nthrough the output ports, from formal part to the actual?\n\nI see a similar double standard in the driving value definition. It says\nthat if signal source is a port then formal part driver is used. You\ncannot drive the input port this way but this is not necessary -\neffective values are rather propagated downwards. We first propagate\ninfo upwards through output ports by driving values and then signals\npropagate downwards as effective values. Right? I see no such\nbi-directional mechanism for the signal activity propagation.\n\n\n=2= Moreover, I do not see how the signal activity flag is connected to\nanything else. For instance, I see how driver's value originates from\nthe transaction, how this determines the driving values of signals and,\nfurthermore, the effective values. However, I see that all what\ndetermines the signal activity flag is the activity flag of another\nsignal! I want to know how is the first active signal can ever appear in\nsuch system?\n\n\n=3= Ports are also sources. Why sources and ports are treated\nseparately? BTW, why not to instantiate the drivers for the ports also?\nTo avoid delta-cycle delays in ports?\n\n=4= BTW, is slice a signal?\n\nI have such a mess in my head. Will Ashenden fix it?