barrel shifter 2

Discussion in 'VHDL' started by Hendrik Greving, Dec 5, 2005.

  1. hi,

    does anybody know where to obtain the algorithm of how to make a
    synthesis of a constant barrel shifter, or knows a paper that deals with
    this issue?

    e.g. result = 00011101 << b

    is optimized by combining the b input bits for the output "result"
    instead of using multiplexers.

    Regards,
    Hendrik Greving
     
    Hendrik Greving, Dec 5, 2005
    #1
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  2. Mike Treseler, Dec 5, 2005
    #2
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  3. Hendrik Greving, Dec 8, 2005
    #3
  4. Sorry.
    I don't write synthesis software.
    I use it.
    However, you can learn a lot about it
    by running some code through and
    viewing the rtl schematic.
    Change constraints. Repeat.

    -- Mike Treseler
     
    Mike Treseler, Dec 8, 2005
    #4
  5. :)

    A cadence guy in the verilog newsgroup gave an excellent answer. It's a
    problem of simplifying the combinational truth table of the signal
    sequences of each output bit that give 1 and of the b input.

    Hendrik
     
    Hendrik Greving, Dec 9, 2005
    #5
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