Ashani Patel a écrit :
Start by posting your code
Nicolas
here's my code
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ashani Patel
--
-- Create Date: 20:38:00 05/17/2008
-- Design Name:
-- Module Name: to_integer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: converts 4 bit number to integer.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity to_integer is
generic ( M : integer:= 4 );
Port ( bit_data : in STD_LOGIC_VECTOR (M-1 downto 0);
msb : out std_logic_vector(6 downto 0));
end to_integer;
architecture Behavioral of to_integer is
signal value : integer :=0;
begin
process(bit_data)
variable int_value : integer range 0 to 15:=0; -- i have put this
range for 4 bit
-- otherwise it doesnt get mapped. if i have to make this generic i
cant put this restriction.
-- what is the solution for that.
begin
for N in 0 to M-1 loop
if(bit_data(N) = '1') then
int_value := int_value + 2**N;
end if;
end loop;
value <= int_value;
end process;
process(value)
begin
case value is
when 0 => msb<="1111110";
when 1 => msb<="0011000";
when 2 => msb<="0110111";
when 3 => msb<="0111101";
when 4 => msb<="1011001";
when 5 => msb<="1101101";
when 6 => msb<="1001111";
when 7 => msb<="0111000";
when 8 => msb<="1111111";
when 9 => msb<="1111001";
when others => null;
end case;
end process;
end Behavioral;
