Problem with bcd conversion

[Manaryu]

Hey,

I've run into some problems while designing my first project. (basically the input is a square wave with 3.3 V down to 0 V and I want to have an output on 4 7seg leds.)

So I convert the high/low input to a binary number, convert it to bcd (15 digits as the signal is in the MHz to GHz range) and display these numbers.

For the bcd conversion I've been trying to implement something like the one from xilinx, XAPP029. (relevant portion of my code is below) When I'm running the code on the board, it seems to continuously create new numbers. I'm not quite sure how I can implement/change it so that it calculates the right number.

Any help would be more than welcome as I'm kind of stuck in the middle of my work there.

--bcd conversion  (Part of top module)
		
input <= "00011100000100100010000001010101100101101100111111"; --test input

process (Clock)
begin
	if rising_edge(Clock) and input /= (input'range => '0') then
		for J in 1 to 50 loop
			ModIn <= input(J);
			if J = 50 then
				ModOut <= Modzw;
			end if;
		end loop;
	end if;
end process;



Conv : BcdShift
port map(
		clk => clk,
		ModIn => ModIn,
		ModOut => Modzw,
		Qin => Q,
		Q => Q);
		
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity BcdShift is

    Port (  clk : in std_logic;
       	ModIn  : in std_logic;
	ModOut : out std_logic;
	Qin    : in std_logic_vector(59 downto 0);
	Q      : out  STD_LOGIC_vector(59 downto 0));
end BcdShift;

architecture Behavioral of BcdShift is

component BcdDigit is
	Port (clk : in  STD_LOGIC;
           ModIn  : in  STD_LOGIC;
           ModOut : out  STD_LOGIC;
	   Bcd    : in std_logic_vector (3 downto 0);
           Qb     : out  STD_LOGIC_VECTOR (3 downto 0));
end component;



signal Vect : std_logic_vector(1 to 16) := (others => '0');

begin

Vect(1) <= ModIn;


gen : for i in 1 to 15 generate
  dig: BcdDigit
        port map
        (clk    => clk,
        ModIn   => Vect(I),
        ModOut  => Vect(I+1),
	Bcd     => Qin((I*4)-1 downto (I*4)-4),
        Qb      => Q((I*4)-1 downto (I*4)-4));
  end generate;
  

ModOut <= Vect(16);


end Behavioral;

--------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BcdDigit is
    Port ( clk    : in  STD_LOGIC;
           ModIn  : in  STD_LOGIC;
           ModOut : out  STD_LOGIC;
	   Bcd    : in   std_logic_vector (3 downto 0);
           Qb     : out  STD_LOGIC_VECTOR (3 downto 0));
end BcdDigit;

architecture Behavioral of BcdDigit is
begin
   process(clk)
	begin
	   if rising_edge( clk) then
				case Bcd is
					when "0000" => Qb <= "000" & ModIn;  -- 0*2 + ModIn
					when "0001" => Qb <= "001" & ModIn;  -- 1*2 + ModIn
					when "0010" => Qb <= "010" & ModIn;  -- 2*2 + ModIn
					when "0011" => Qb <= "011" & ModIn;  -- 3*2 + ModIn						
					when "0100" => Qb <= "100" & ModIn;  -- 4*2 + ModIn
					when "0101" => Qb <= "000" & ModIn;  -- 5*2 + ModIn (ModOut=1)
					when "0110" => Qb <= "001" & ModIn;  -- 6*2 + ModIn (ModOut=1)
					when "0111" => Qb <= "010" & ModIn;  -- 7*2 + ModIn (ModOut=1)
					when "1000" => Qb <= "011" & ModIn;  -- 8*2 + ModIn (ModOut=1)						
					when "1001" => Qb <= "100" & ModIn;  -- 9*2 + ModIn (ModOut=1)
					when others => Qb <= "0000";						
				end case;
		end if;	
	end process;
	
	ModOut <= '1' when Bcd>=5 else '0';

end Behavioral;

 

[Manaryu]

Forgot to mention that clk is the system clock (in my case 10 MHz) and Clock is a 50 Hz clock.

Also I've been trying around with "next when" in the loop on the top level. Wanted to limit it so that it calculates exactly the required number of "shift / add 3" and doesnt continue on with input(50) as I suspect it to do at the moment. But couldnt get any improved results out of it.

Cheers.