need help ! conversion BCD to Bin

[lusefar]

Hi,

im writing (learning how to write) a conversion Bin to BCD and BCD to Bin , i have read a lot about how to convert Bin to Bcd (add 3 algorithm) , i konw the Conversion Bcd to Bin reverses the Bin-to-Bcd conversion process. but somehow i failed with it. i dont know how to realize this reverse. can someone help me plz.

hier is the exampel code Bin-to-Bcd :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BinzuBCD is
Port ( Clk : in STD_LOGIC;
Init : in STD_LOGIC;
Rst: in STD_LOGIC;
ModIn : in STD_LOGIC;
ModOut : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end BinzuBCD;

architecture Behavioral of BinzuBCD is
signal Bcd: STD_LOGIC_VECTOR (3 downto 0);
begin
process( Clk,Init)
begin
if rising_edge( Clk) then
if Init='1' then
Bcd <= "0000";
elsif Rst='0' then
case Bcd is
when "0000" => Bcd <= "000" & ModIn; -- 0*2 + ModIn
when "0001" => Bcd <= "001" & ModIn; -- 1*2 + ModIn
when "0010" => Bcd <= "010" & ModIn; -- 2*2 + ModIn
when "0011" => Bcd <= "011" & ModIn; -- 3*2 + ModIn
when "0100" => Bcd <= "100" & ModIn; -- 4*2 + ModIn
when "0101" => Bcd <= "000" & ModIn; -- 5*2 + ModIn (ModOut=1)
when "0110" => Bcd <= "001" & ModIn; -- 6*2 + ModIn (ModOut=1)
when "0111" => Bcd <= "010" & ModIn; -- 7*2 + ModIn (ModOut=1)
when "1000" => Bcd <= "011" & ModIn; -- 8*2 + ModIn (ModOut=1)
when "1001" => Bcd <= "100" & ModIn; -- 9*2 + ModIn (ModOut=1)
when others => Bcd <= "0000";
end case;
end if;
end if;
end process;

ModOut <= '1' when Bcd>=5 else '0';
Q <= Bcd;

end Behavioral;






library IEEE;
use IEEE.std_logic_1164.all;

entity BCDwandler is
generic (N : integer :=3);
port (Clk : in std_logic;
Rst : in std_logic;
Init : in std_logic; -- initialisierung
ModIn : in std_logic; -- carry in
ModOut : out std_logic; -- carry out
Q : out std_logic_vector(4*N -1 downto 0) -- BCD Ergebnis
);
end;

architecture arch of BCDwandler is

component BinzuBCD is
port (Clk : in std_logic;
Rst : in std_logic;
Init : in std_logic;
ModIn : in std_logic;
ModOut : out std_logic;
Q : out std_logic_vector(3 downto 0)
);
end component;

signal ModBreite : std_logic_vector(1 to N+1);

begin


BCDAnzahl : for i in 1 to N generate
Rgs: BinzuBCD
port map
(Clk => Clk,
Rst => Rst,
Init => Init,
ModIn => ModBreite(I+1),
ModOut => ModBreite(I),
Q => Q(I*4-1 downto I*4-4));
end generate;

ModOut <= ModBreite(1);
ModBreite(N+1) <= ModIn;

end;