Cyclone II PCI & pin swapping

[joey]

I'm implementing a PCI104+ board which will have the opencores PCI
bridge core. I've started with the suggested layout from Alteras PCI
Megacore. But the choice of pins does not lend to a really clean
layout. If I swap some of the pins around it will clean up quite a
bit. I'm wondering if I'm asking for timing problems if I do this.
I'm only planning to run the PCI at a leasurely 33Mhz, so I'm guessing
it won't be a problem, as long as I keep it in the same pair of banks
(5 & 6). Any thoughts or suggestions?

Many thanks

Joey

 

[Charles Steinkuehler]

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I'm implementing a PCI104+ board which will have the opencores PCI
bridge core. I've started with the suggested layout from Alteras PCI
Megacore. But the choice of pins does not lend to a really clean
layout. If I swap some of the pins around it will clean up quite a
bit. I'm wondering if I'm asking for timing problems if I do this.
I'm only planning to run the PCI at a leasurely 33Mhz, so I'm guessing
it won't be a problem, as long as I keep it in the same pair of banks
(5 & 6). Any thoughts or suggestions?

The cyclone parts should have no real problems running at 33 MHz, but
the hardest part of the PCI timing specs for FPGAs to meet is typically
the setup/hold times. I've also not tried using the opencores PCI
bridge with Altera FPGAs (my experience is with the Altera PCI core),
and there can be quite a bit of combinatorial logic between the on-chip
flip-flops and the external PCI I/O pins (which is a big part of why
it's hard for FPGAs to meet the PCI timing specs).

I suggest you fully enter the PCI timing specs and do a test compile
with both the Altera pinout and with your desired changes. I suspect
you'll be able to move some pins around without major negative consequences.

NOTE: I'm not sure if it's still required (we've migrated to PCIe), but
with the older (ie: 10K/20K) parts, it was necessary to route some of
the PCI signals to high-speed global inputs...you might (or might not,
especially at 33 MHz) have to do this with the opencores bridge, but
it's something to be aware of.

- --
Charles Steinkuehler
(e-mail address removed)

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[Charles Steinkuehler]

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The cyclone parts should have no real problems running at 33 MHz, but
the hardest part of the PCI timing specs for FPGAs to meet is typically
the setup/hold times.

....and clk to out times. Make sure you appropriately constrain the
clk->out paths when running the timing simulator.

- --
Charles Steinkuehler
(e-mail address removed)

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