I am trying to design a 2-bit adder in tree format. The design looks like as: Four 2-bit Full adders at top, than three 3-bit FA at second stage, than 2 4-bit FA at third stage. In final single 5-bit FAs.
2-bit FA with 3-bit output is developed by considering carry-out as data bit.
1. Problem is how to develop other 3 2-bit FA in single row?
2. & than float the output arguments of first row i.e. sum0[0..2], sum1[0...2], sum2[0...2], sum3[0...2] as inputs for the next row having 3 3-bit FA. & so on.
final shape of the design will look like a traingle.
Could any one helpout in this regad?
shan
2-bit FA with 3-bit output is developed by considering carry-out as data bit.
1. Problem is how to develop other 3 2-bit FA in single row?
2. & than float the output arguments of first row i.e. sum0[0..2], sum1[0...2], sum2[0...2], sum3[0...2] as inputs for the next row having 3 3-bit FA. & so on.
final shape of the design will look like a traingle.
Could any one helpout in this regad?
shan