8 bit full adder 2's complement

Discussion in 'VHDL' started by salvador1985, Apr 19, 2009.

  1. salvador1985

    salvador1985

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    Hello everybody!

    I am struggling with this project.

    I need to design a Full Adder circuit which has 8-bit 2's complement numbers as input and which is capable of adding them. Also I need to have an overflow flag in order to detect if overflow occurs.

    This is my code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.NUMERIC_STD.all;

    --entity declaration
    entity FA_OF is
    port (A, B : in signed(7 downto 0);
    Cin : in signed;
    sum : out signed(7 downto 0);
    Cout : out signed;
    overflow_flag : out signed);
    end entity FA_OF;

    --architecture body
    architecture ARCH2 of FA_OF is

    begin

    process

    begin

    sum <= (A xor B) xor Cin;
    Cout <= ((A and B) or ( (A xor B) and Cin));

    --overflow control
    --if the most significant bit of A is equal to the MSB of B
    --check that they have the same sign as the MSB of Cout has
    --otherwise assume that overflag occurs
    --and set flag to be HIGH

    if (A(7) = B(7)) and (a(7) /= Cout) then
    overflow_flag <= '1';
    else overflow_flag <= '0';
    end if;
    wait;
    end process;

    end ARCH2;

    ----

    here to find out the overflow I am taking the Most significant bit of A and B. If they are equal then compare it to the Carry. If they are not equal then overflow occurs.

    I am not sure on with type use, signed, unsigned, etc.. not sure of it at all.
    Also how can I get the MSB of a signed number? By saying 7 downto 6 for example I get 2 numbers instead of 1.
    Also I think I am not actually considering the Full adder for 8 bit but only for 1 bit. How can I change it to work for 8 - bit? I am actually getting crazy with this..

    Can anyone help me?

    Thank you

    Salvador
     
    salvador1985, Apr 19, 2009
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  2. salvador1985

    jeppe

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    jeppe, Apr 20, 2009
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  3. salvador1985

    salvador1985

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    Thank you Jeppe I actually managed to move on and create correctly I think a 8 bit full adder which is using 2 ' s complement as inputs..

    but now I got a problem in the row 63:

    "cannot read output sum".

    I need to compare the Most significant bit of input A and input B with the MSB of the ouput S. if A(7)=B(7) and A(7)/=Sum(7)
    then overflow occurs

    can anyone check what I am doing wrong please?

    the code is as follows:

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.NUMERIC_STD.all;

    --entity declaration
    entity FA_OF is
    port (A, B : in signed(7 downto 0);
    Cin : in std_logic;
    sum : out signed(7 downto 0);
    Cout : out std_logic;
    overflow_flag : out std_logic);
    end entity FA_OF;

    --architecture body
    architecture ARCH2 of FA_OF is

    component FullAdder2
    port(
    Ax : in std_logic;
    Bx : in std_logic;
    Cin : in std_logic;
    Sx : out std_logic;
    Cout : out std_logic);
    end component;

    signal carry : signed(8 downto 0);

    begin

    carry(0) <= Cin;

    Adder32:
    for i in 0 to 7 generate
    FAx : FullAdder2 port map(
    Ax => A(i),
    Bx => B(i),
    Cin => Carry(i),
    Sx => Sum(i),
    Cout => Carry(i+1));

    end generate;

    Cout <= Carry(8);

    process

    begin

    --overflow control
    --if the most significant bit of A is equal to the MSB of B
    --check that they have the same sign as the MSB of Cout has
    --otherwise assume that overflag occurs
    --and set flag to be HIGH

    if ((A(7) = B(7)) and (A(7) /= Sum(7))) then
    overflow_flag <= '1';
    else overflow_flag <= '0';
    end if;
    wait;
    end process;

    end ARCH2;

    I wrote in RED the line which gives me the error as said above.

    Many thanks in advance!8)
     
    salvador1985, Apr 20, 2009
    #3
  4. salvador1985

    jeppe

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    Hi Salvator

    first change this line:
    sum : out signed(7 downto 0);
    to
    sum : inout signed(7 downto 0);

    besides will this be more correct VHDL:

    Code (Text):
    process (A,B,Sum)
    begin

    --overflow control
    --if the most significant bit of A is equal to the MSB of B
    --check that they have the same sign as the MSB of Cout has
    --otherwise assume that overflag occurs
    --and set flag to be HIGH

       if ((A(7) = B(7)) and (A(7) /= Sum(7))) then
           overflow_flag <= '1';
       else
           overflow_flag <= '0';
       end if;
       --wait   will stop the process for infinity;
    end process
    Your welcome
    Jeppe
     
    jeppe, Apr 20, 2009
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  5. salvador1985

    salvador1985

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    thanks Jeppe! Now it is working!!8)
     
    salvador1985, Apr 20, 2009
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