OK, thanks a lot. Got it. I'm telling it that various flip flops need to
be clocked by two different clocks, and I can't expect the tool to work
out how to combine the clocks when I haven't even thought of how to it
myself.
It's actually worse than that. As someone else pointed out, your
code is effectively doing this...
process (clk1, clk2)
begin
if rising_edge(clk1) then
....
if rising_edge(clk2) then
...
Note that you're not WAITING for the rising edge of clk2,
but only TESTING it; so the second "if" can succeed only if
both rising edges occur exactly simultaneously. Exact
simultaneity does have a sensible meaning in discrete-event
simulation, but of course it cannot be realised in hardware.
In simulation-only code I could reasonably write...
process -- no sensitivity list
begin
wait until rising_edge(clk1);
.... -- do some stuff
wait until rising_edge(clk2);
.... -- do some more stuff
wait until falling_edge(clk2) or rising_edge(clk1);
..... -- and so on.
end process;
But of course there is no chance of synthesising
such a thing to hardware.
You might care to read my recent response to the thread
"johnson ring counter and how to simulate it" for an
extended rant about synchronous design, and how to
detect transitions synchronously.
In this context, is there any way of telling it that a signal is always
to be considered asynchronous, and that it shouldn't ever be a flipflop?
Signals get implemented as flipflops in VHDL for one reason only:
because you write to them on the rising edge of a clock, and
at no other time.
To make a signal that will be synthesised to asynchronous
(combinational) logic, you must write to it from a combinational
process - one in which the outputs are calculated as a pure
function of the inputs, and are recalculated whenever any one
(or more) of the inputs changes:
process (list, your, inputs, here)
begin
output1 <= list and inputs;
if here = '1' then
output2 <= your;
else
output2 <= '0';
end if;
end process;
Note the rules for a combinational process:
- every input goes in the sensitivity list
- every output is given a new value whenever the
process executes
- no feedback (don't use outputs as inputs)
Reconsider how you could solve your problem using a single,
fast master clock and fully synchronous logic.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.