dqpsk decoder

[cruzer]

Hi, im new to vhdl coding. I want to implement a dqpsk precoder using two D flip flops.
however,im not able to synthesize the code successfully. It shows some errors.
The code and diagram are attached. the errors found are:
ERROR:HDLParsers:3312 - "C:/Xilinx/10.1/ISE/MAIN/mainproj/precoder.vhd" Line 54. Undefined symbol 'c'.
ERROR:HDLParsers:1209 - "C:/Xilinx/10.1/ISE/MAIN/mainproj/precoder.vhd" Line 54. c: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Xilinx/10.1/ISE/MAIN/mainproj/precoder.vhd" Line 55. Undefined symbol 'q'.

Why isn't the code getting synthesized successfully?
i've marked line 54 and 55 in the attached file

 

[eliascm]

logic

I am not familiar with a package called IEEE.STD_LOGIC_UNSIGNED. Did you mean to use numeric_std? However, I think your main problem is that there is not an entity/architecture for component comb.

 

[jeppe]

Try this

I believe you got some problems with the definitions of components - try this

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity precod is
      Port (clk, x, y : in std_logic;
      i, q : out std_logic);
end precod;

architecture Behav of precod is
   signal i0, q0, i1, q1 : std_logic;
   
   component dff is
   port( D, Clk : in std_logic;
         D_out :  out std_logic);
         end component;

   component comb is
   port(  a, b, c, d : in std_logic;
           i, q : out std_logic);
   end component;

begin
   C1:comb port map( x,y,i1,q1,i0,q0); 
   D1:dff  port map (i0,Clk,i1);
   D2:dff  port map( q0,Clk,q1);
   i <= i0;
   q <= q0;
end Behav;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
   Port (   D : in std_logic;
            Clk : in std_logic;
            D_out : out std_logic);
end dff;

architecture Behav of dff is
begin
   process(Clk)
   begin
      if (Clk'event and Clk = '1') then
         D_out <= D;
      end if;
   end process;
end Behav;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comb is
   port(  a, b, c, d : in std_logic;
           i, q : out std_logic);
end comb;

architecture Behav of comb is
   signal j,k,l,m : std_logic;
begin
   j<=not a;
   k<=not b;
   l<=not c;
   m<=not d;
   i <=  '1' when ((j='1' and l='1' and m='1') or 
                   (k='1' and l='1' and m='1') or 
                   (a='1' and c='1' and d='1') or 
                   (b='1' and c='1' and m='1')) else '0';  ---LINE 54
   q <= '1' when   ((k='1' and l='1' and m='1') or 
                   (a='1' and l='1' and d='1') or
                   (b='1' and c='1' and d='1') or 
                   (j='1' and c='1' and m='1')) else '0';  ---LINE 55
end Behav;

-- Alternative version of comb
architecture Behav2 of comb is
   signal abcd: std_logic_vector ( 3 downto 0);
begin
   abcd <= a&b&c&d;
   with abcd select       -- Truth table / ramdom content
   i <= '0' when "0000",
        '1' when "0001",
        '1' when "0010",
        '0' when "0011",
        '1' when "0100",
        '1' when "0101",
        '1' when "0110",
        '0' when "0111",
        '1' when "1000",
        '1' when "1001",
        '0' when "1010",
        '1' when "1011",
        '1' when "1100",
        '0' when "1101",
        '1' when "1110",
        '0' when others;
   with abcd select        -- Truth table / ramdom content
   q <= '1' when "0000",
        '0' when "0001",
        '1' when "0010",
        '0' when "0011",
        '1' when "0100",
        '1' when "0101",
        '1' when "0110",
        '0' when "0111",
        '1' when "1000",
        '1' when "1001",
        '0' when "1010",
        '1' when "1011",
        '1' when "1100",
        '0' when "1101",
        '1' when "1110",
        '0' when others;
end Behav2;

your welcome