Y
Yiðit Tuncel
Hello,
I'm trying to design a small project, that is scrolling a text that is entered from keyboard on the 7 segment display of BASYS2 board. I am near the end, but having some compiling issues. I am thinking that the problem arisesfrom a package I declared, that includes the type "array of bytes". The shifter module I wrote uses this type, but there are some errors with it. Basically, cpu does not locate the type I declared in the package.
Here's the shifter module:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.mypackage2.all;
entity shifter is
generic ( REGSIZE : integer := 16);
port(clk : in std_logic;
Scan_Dav : in std_logic;
Data_in : in std_logic_vector(7 downto 0);
Data_out : out reg_array(REGSIZE-1 downto 0));
end shifter;
architecture bhv of shifter is
signal shift_reg : reg_array(REGSIZE-1 downto 0); --:= (others<='0');
begin
process (clk, Scan_Dav) begin
if rising_edge(clk) then
if Scan_Dav then
shift_reg(REGSIZE-1 downto 1) <= shift_reg(REGSIZE-2 downto 0);
shift_reg(15) <= shift_reg(0);
end if;
end if;
Data_out <= shift_reg;
end process;
end bhv;
Here's the package:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mypackage2 is
subtype reg is std_logic_vector(7 downto 0); -- a byte
type reg_array is array (0 to 15) of reg; -- array of bytes
end mypackage2;
package body mypackage2 is
end mypackage2;
As I'm new to VHDL, I might have done some basic errors. Also, the package I've written does not show up in the project hierarchy at the lefthand sideof the window.
And these are the errors:
ERROR:HDLParsers:524 - "F:/Projeilk/Shifter.vhd" Line 12. reg_array is already a constrained array type.
ERROR:HDLParsers:3010 - "F:/Projeilk/Shifter.vhd" Line 15. Entity shifter does not exist.
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 17. Undefined symbol'reg_array'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 17. reg_array: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 17. Undefined symbol'REGSIZE'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 17. REGSIZE: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 19. Undefined symbol'clk'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 19. clk: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 19. Undefined symbol'Scan_Dav'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 19. Scan_Dav: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 20. Undefined symbol'rising_edge'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 20. rising_edge: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 22. Undefined symbol'shift_reg'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 22. shift_reg: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 26. Undefined symbol'Data_out'.
I'm trying to design a small project, that is scrolling a text that is entered from keyboard on the 7 segment display of BASYS2 board. I am near the end, but having some compiling issues. I am thinking that the problem arisesfrom a package I declared, that includes the type "array of bytes". The shifter module I wrote uses this type, but there are some errors with it. Basically, cpu does not locate the type I declared in the package.
Here's the shifter module:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.mypackage2.all;
entity shifter is
generic ( REGSIZE : integer := 16);
port(clk : in std_logic;
Scan_Dav : in std_logic;
Data_in : in std_logic_vector(7 downto 0);
Data_out : out reg_array(REGSIZE-1 downto 0));
end shifter;
architecture bhv of shifter is
signal shift_reg : reg_array(REGSIZE-1 downto 0); --:= (others<='0');
begin
process (clk, Scan_Dav) begin
if rising_edge(clk) then
if Scan_Dav then
shift_reg(REGSIZE-1 downto 1) <= shift_reg(REGSIZE-2 downto 0);
shift_reg(15) <= shift_reg(0);
end if;
end if;
Data_out <= shift_reg;
end process;
end bhv;
Here's the package:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mypackage2 is
subtype reg is std_logic_vector(7 downto 0); -- a byte
type reg_array is array (0 to 15) of reg; -- array of bytes
end mypackage2;
package body mypackage2 is
end mypackage2;
As I'm new to VHDL, I might have done some basic errors. Also, the package I've written does not show up in the project hierarchy at the lefthand sideof the window.
And these are the errors:
ERROR:HDLParsers:524 - "F:/Projeilk/Shifter.vhd" Line 12. reg_array is already a constrained array type.
ERROR:HDLParsers:3010 - "F:/Projeilk/Shifter.vhd" Line 15. Entity shifter does not exist.
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 17. Undefined symbol'reg_array'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 17. reg_array: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 17. Undefined symbol'REGSIZE'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 17. REGSIZE: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 19. Undefined symbol'clk'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 19. clk: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 19. Undefined symbol'Scan_Dav'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 19. Scan_Dav: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 20. Undefined symbol'rising_edge'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 20. rising_edge: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 22. Undefined symbol'shift_reg'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 22. shift_reg: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 26. Undefined symbol'Data_out'.