dual edge

[raullim7]

i know i have posted this topic a number of times but this time its
bcos of something new that i was told to do..

i am having a counter that counts from 0 to 99, now i want to increase
the count to 0 to 199. however, i am not able to increase the
frequency, its a restriction. what i did was using dual edge behavior.
previously for 0 to 99, it only triggers during the rising edge, so
now i want to use the falling edge to take on another 100 counts. but
xilinx does not allow me to use two clock within a single process. so
now i have two process to take care of the rising and the falling
edge.

the mistake that i found is that my code is still doing 0 to 99. bcos
i cant integrate the two process together. each of them will do 0 to
99 individually. as my code is intended to run a control system that
will vary a variable as the counter runs from 0 to 199.

process1 (rising edge)
if (counter1 >= 99 )
counter1 = 0
else
counter1 = counter1 + 1;

process2 (falling edge)
if (counter2 >= 99)
counter2 = 0
else
counter2 = counter2 + 1

i tried to use a gobal variable for counter1 and counter2 so that only
1 counter is counting but is not able to compile.

for example 0 to 199, i want to check something at counter = 50, i
will not be able to get the correct result as i am only able to get
counter1= 50 or counter2=50 which is incorrect. the thing that i
wanted to check will run randomly from 0 to 199, so i am not able to
fix it and use some formulas to check it.

is there any ways to resolve my problem? kindly help and advise..
thank you very much..

 

[Andy]

i know i have posted this topic a number of times but this time its
bcos of something new that i was told to do..

i am having a counter that counts from 0 to 99, now i want to increase
the count to 0 to 199. however, i am not able to increase the
frequency, its a restriction. what i did was using dual edge behavior.
previously for 0 to 99, it only triggers during the rising edge, so
now i want to use the falling edge to take on another 100 counts. but
xilinx does not allow me to use two clock within a single process. so
now i have two process to take care of the rising and the falling
edge.

the mistake that i found is that my code is still doing 0 to 99. bcos
i cant integrate the two process together. each of them will do 0 to
99 individually. as my code is intended to run a control system that
will vary a variable as the counter runs from 0 to 199.

process1 (rising edge)
if (counter1 >= 99 )
counter1 = 0
else
counter1 = counter1 + 1;

process2 (falling edge)
if (counter2 >= 99)
counter2 = 0
else
counter2 = counter2 + 1

i tried to use a gobal variable for counter1 and counter2 so that only
1 counter is counting but is not able to compile.

for example 0 to 199, i want to check something at counter = 50, i
will not be able to get the correct result as i am only able to get
counter1= 50 or counter2=50 which is incorrect. the thing that i
wanted to check will run randomly from 0 to 199, so i am not able to
fix it and use some formulas to check it.

is there any ways to resolve my problem? kindly help and advise..
thank you very much...

In your example, the total "count" is the sum of both counters, which
will get up to 198.

You could also cross-couple two counters, one on each clock. Each
counter stores the increment of the OTHER counter.

Brute force, it could be done as follows:

re: process (clk) is
begin
if rising_edge(clk) then
if counter2 >= 199 then
counter1 <= 0;
else
counter1 <= counter2 + 1;
end if;
end if;
end process re;

fe: process (clk) is
begin
if falling_edge(clk) then
if counter1 >= 199 then
counter2 <= 0;
else
counter2 <= counter1 + 1;
end if;
end if;
end process fe;

Andy

 

[filmil]

is there any ways to resolve my problem? kindly help and advise..
thank you very much..

Why not use a single counter clocked on the rising edge of the clock,
then use the counter binary representation as (most_significant_bit
downto 1) and the clk value itself as bit 0?

f

 

[ghelbig]

i know i have posted this topic a number of times but this time its
bcos of something new that i was told to do..

i am having a counter that counts from 0 to 99, now i want to increase
the count to 0 to 199. however, i am not able to increase the
frequency, its a restriction. what i did was using dual edge behavior.
previously for 0 to 99, it only triggers during the rising edge, so
now i want to use the falling edge to take on another 100 counts. but
xilinx does not allow me to use two clock within a single process. so
now i have two process to take care of the rising and the falling
edge.

the mistake that i found is that my code is still doing 0 to 99. bcos
i cant integrate the two process together. each of them will do 0 to
99 individually. as my code is intended to run a control system that
will vary a variable as the counter runs from 0 to 199.

process1 (rising edge)
if (counter1 >= 99 )
counter1 = 0
else
counter1 = counter1 + 1;

process2 (falling edge)
if (counter2 >= 99)
counter2 = 0
else
counter2 = counter2 + 1

i tried to use a gobal variable for counter1 and counter2 so that only
1 counter is counting but is not able to compile.

for example 0 to 199, i want to check something at counter = 50, i
will not be able to get the correct result as i am only able to get
counter1= 50 or counter2=50 which is incorrect. the thing that i
wanted to check will run randomly from 0 to 199, so i am not able to
fix it and use some formulas to check it.

is there any ways to resolve my problem? kindly help and advise..
thank you very much..

Our friend Ralf has published "The Pseudo Dual-Edge D-Flipflop". Easy
Google search.

Don't be tempted to just combine clock and Q combinatorially; OK for
simulation, but it will glitch in real life.

G.

 

[Andy]

Why not use a single counter clocked on the rising edge of the clock,
then use the counter binary representation as (most_significant_bit
downto 1) and the clk value itself as bit 0?

f

hold time violation on bit 0 (lsb) destination?

Compatibility with static timing analysis? (it may work, I dunno)

Or just create a single bit, dual-edge counter as above for lsb, and
single clock counter for the rest of the bits, assuming the counter
increments every clock.

Andy

 

[raullim7]

In your example, the total "count" is the sum of both counters, which
will get up to 198.

You could also cross-couple two counters, one on each clock. Each
counter stores the increment of the OTHER counter.

Brute force, it could be done as follows:

re: process (clk) is
begin
if rising_edge(clk) then
if counter2 >= 199 then
counter1 <= 0;
else
counter1 <= counter2 + 1;
end if;
end if;
end process re;

fe: process (clk) is
begin
if falling_edge(clk) then
if counter1 >= 199 then
counter2 <= 0;
else
counter2 <= counter1 + 1;
end if;
end if;
end process fe;

Andy- Hide quoted text -

- Show quoted text -

my FPGA card is running at 100MHZ. i am restricting it too 100 counts
per cycle to get 1us period per cycle. if i increase my counts to 199,
i will not be getting 1us period which is a must. to elaborate, for
example for the positive edge of 100 counts, i am setting a duty cycle
with it. that is if it is counting at 50, i will get a duty ratio of
50/100 = 50%. now i am only able to get duty ratio of 10%, 11%, 12%,..
all whole numbers.. my intention is to be able to get duty ratio of
10%, 10.5%, 11%, 11.5%, 12%,.... that is why i need to integrate both
the positive and negative counts together. pls help. thanks

 

[jens]

my FPGA card is running at 100MHZ. i am restricting it too 100 counts
per cycle to get 1us period per cycle. if i increase my counts to 199,
i will not be getting 1us period which is a must. to elaborate, for
example for the positive edge of 100 counts, i am setting a duty cycle
with it. that is if it is counting at 50, i will get a duty ratio of
50/100 = 50%. now i am only able to get duty ratio of 10%, 11%, 12%,..
all whole numbers.. my intention is to be able to get duty ratio of
10%, 10.5%, 11%, 11.5%, 12%,.... that is why i need to integrate both
the positive and negative counts together. pls help. thanks

Now that we know the actual requirements, it's a lot easier to help!

The solution is pretty simple: create a 100-count rising edge counter
to produce a whole number duty cycle counter. Feed the output of that
counter into a single falling edge flip-flop, so now there's a signal
delayed by 0.5% duty cycle. OR the two signals together (the counter
output and the delayed output), and that will produce a N.5% duty
cycle signal. Use a mux to select either the N% duty cycle or N.5%
signal. That should work for all but 0.5%.