how to convert real type to std_logic_vector ?

[jing]

i'm a beginner in vhdl. please tell me how to convert real type to
std_logic_vector ?
i wrote as:

process
variable input_line : line;
variable input_data : real;
begin
i <= 0;
xn_re <= "0000000000000000";

while not endfile(DATA_FILE) loop
readline(DATA_FILE, input_line);
read(input_line, input_data);

xn_re <= std_logic_vector(to_signed(integer(input_data),
16));-----here is the problem,but if i use xn_re <=
conv_std_logic_vector(input_data, 16); the input_data should not be a
real type....., then i don't know how to solve it.....

thank you in advace!

 

[Mike Treseler]

i'm a beginner in vhdl. please tell me how to convert real type to
std_logic_vector ?

http://groups.google.com/groups/search?q=vhdl+math_real+std_logic_vector