how to implement gated clock and gated partial circuit in VHDL?

Discussion in 'VHDL' started by walala, Sep 20, 2003.

  1. walala

    walala Guest

    Dear all,

    I heard about a quite effective low power technique buzzword: "gated clock"
    and/or "gated" sub-circuit for long. But I don't know how to implement this
    in VHDL? Can anybody point me to some resources which have
    easy-to-understand and practical samples or template that I can follow...?

    Thanks a lot,

    walala, Sep 20, 2003
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  2. walala

    Roadie Roger Guest

    Actually gating clocks is relatively evil. Having a gated clock that
    transitions less often does save power. Every signal edge is a power
    waster in the face of capacitance. Gated clocks create other
    problems. Your clocks are no longer exactly lined up. Many chips
    have a global clock that goes everywhere. Breaking it into pieces
    isn't a good thing. You want to enable data rather than gate clocks.
    Call the Enable 'E'. This looks something like:

    If CLK'event and CLK = '1' then
    Q <= (not(E) and Q) or (D and Q) or (D and E);
    end if;

    I realize this doesn't tell you how to gate clocks. I'm not gonna
    tell you, because I can't tell you how to fix the problems it creates.

    Happy Designing,
    Roadie Roger
    Roadie Roger, Sep 22, 2003
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  3. I heard about a quite effective low power technique buzzword: "gated clock"
    Depends on your target technology. The above may hold for FPGA's,
    but for standard-cell based ASIC technologies, gated clocks are
    an elegant (in my opinion) and clean methodology for low-power

    In this case, you will most likely be using a clock tree generator
    anyway, and all of the clock tree generators I know easily handle
    clock gates. They will automatically align the clocks AFTER any
    possible gates, i.e. at the leaf nodes (clock inputs of registers).
    In this case, generating a low-skew clock tree is far easier for
    gated clocks than for derived clocks (i.e. divided clocks).

    Modern synthesis tools also can insert clock gates automatically
    by replacing register enables (as shown in the post above) by
    gated clocks. This can be handy, but it has the drawback of
    reducing your control over clock gates (names, hierarchy).

    Inserting clock gates in a VHDL design is easy. Just decide what
    gating style you want/need (and/or based, with/without latch, with
    test bypass, observability, ...).

    My choice is to then explicitly instantiate a clock gating
    element where needed. This has the disadvantage of requiring one
    to "route" different clock signals through the design, but
    it gives you full control over clock gating elements for use
    in later stages of the design (clock tree generation, physical
    optimization, ...).

    Information about "clean" clock gating can be found in books
    or also in synthesis tool manuals (where automatic clock
    gate insertion is described). Probably you'll also find
    resources on the web.

    Robert Reutemann, Sep 23, 2003
  4. walala

    Roadie Roger Guest

    In that case, I withdraw my objection. Go for it :)
    Roadie Roger, Sep 23, 2003
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