latch and flipflop

Discussion in 'VHDL' started by Amit, Jun 8, 2007.

  1. Amit

    Amit Guest

    Hello group,

    How should I create a Latch in VHDL?

    Amit, Jun 8, 2007
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  2. Amit

    Amit Guest

    OK. Let me give you more information. I know how to create a latch in
    VDHL but what I don't know is that since we don't have a clock there
    then how should I implement a situation that has different steps. Or
    let's say an FSM situation?

    All Latch has as input are data_input and enable_ctrl.

    Your help will be appreciated greatly.

    Amit, Jun 8, 2007
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  3. Amit

    JK Guest

    op <= data_input when enable_ctrl='1'; will create latch as expected.
    If you want to have FSM situation on op, update data_input/enable_ctrl
    signals in a FSM.
    This FSM will work clock. ie., enable_ctrl/data_input will
    depend on FSM state.

    Is this what you are expecting??

    JK, Jun 8, 2007
  4. Amit

    Amit Guest

    Hello JK,

    Are you saying that I can use the same FSM structure I have used in a
    FlipFLop for the D-Latch?

    Another words, should I check if the latch is Enable and then some
    predefined values to the output?



    if enable = '0' then
    state_reg <= InitState;
    state_reg <= State1;
    end If;

    end process;

    Thanks for your response and time you spent.

    Amit, Jun 8, 2007
  5. Amit

    JK Guest

    It is like this. Suppose that u r generating latch for signal op.
    op <= data_input when enable_ctrl='1';
    So, your op will be latched to data_input only when enable_ctrl='1';

    Now, if you want FSM kind of states on signal op...

    type states is (st0, st1, st2...);
    signal state : states;

    process(clk, reset)
    if reset='1' then
    state <= st0;
    enable_ctrl <= '0';
    elsif rising_edge(clk) then
    case state is
    when st0 =>
    state <= st1;
    enable_ctrl <= '1';
    when st1 =>
    state <= st2;
    enable_ctrl <= '0';

    Now, you are controlling generation of enable_ctrl a FSM, so
    your signal op will be reflecting FSM states, though it is a latch.

    JK, Jun 8, 2007
  6. Amit

    Amit Guest

    Right here is my problem. I don't have a clock!!! I must do this in
    this entity:

    entity arbiter is

    request: in std_logic_vector(0 to 3);
    reset: in std_logic;
    ack : inout std_logic_vector(0 to 3));

    end entity arbiter;

    as you see there is no clock even no enable signal. how can I
    implement the FSM for this arbiter?

    Amit, Jun 8, 2007
  7. Before doing anything, you need precise requirements of the block you are
    going to design. Is request edge sensitive or level sensitive? How should
    the ack work? Why is it inout in stead of out?
    Why are you so focused on latches? The reasoning "there is no clock, so I
    must use latches" simply does not make any sense.

    Depending on the requirement, I can imagine a design where the request
    inputs are used as a clocks, capturing the positive edges on the request
    inputs. It would not be a nice synchronous design though.
    Paul Uiterlinden, Jun 8, 2007
  8. Amit

    JK Guest

    Amit, then it depends on what you want to send on ack. I guess you may
    not need FSM in this case...

    JK, Jun 8, 2007
  9. Amit

    Amit Guest

    Hi JK,

    But how should I switch from one state to anohter one? if there is no
    need for FSM. Would you give me small sample?

    Amit, Jun 8, 2007
  10. Amit

    willwestward Guest

    The if statement without else part would create a latch. For example,

    if a = '1' and c /= '0' then
    d <= '00'
    elsif a = '0' and c = '0' then
    d <= '01'
    end if;

    Is this enough to get you going?
    willwestward, Jun 8, 2007
  11. Amit

    Amit Guest

    Thanks for sharing it but what is /= operator?

    Amit, Jun 9, 2007
  12. Amit

    willwestward Guest

    /= is does not equal, same as != in C.
    willwestward, Jun 9, 2007
  13. Amit

    Amit Guest

    got it. Thanks

    Amit, Jun 9, 2007
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