limitations on xilinx webpack


D

Dave

Please excuse me if this has been asked before but I'm a newbie...

I've just downloaded and installed Xilinx Webpack 8.1i and updated to
8.1.03i. I'm running through the tutorial for ISE7 (they don't have a
tutorial for ISE8 yet?) and have run into a problem.

I wanted to describe my top-level hierarchy as a schematic with all the
lower level components as VHDL modules. I get the error that the XE version
only support a single HDL.

Is this a limitation with the Webpack version?

I also tried to describe a simple design with a three-input AND gate. It
synthesises without error but when I try to simulate it, I get the same
complaint... the XE version only supports a single HDL.

Is there any way to make a hierarchcial design with a schematic top-level
and VHDL components with Webpack 8.1?

Thanks.

Dave
 
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B

backhus

hi Dave,
it's not directly a problem of ISE 8.1i but Modelsim XE (Starter) is
limited to one type of HDL. Either VHDL or Verilog.

If you are a working on a VHDL Design the ISE 8.1 project navigator
blesses you with some pitfalls. Namely it has set all converting
programs to verilog. You need to change the properties of "View HDL
functional model" and "View HDL instantiation template" to VHDL. Then
cleanup your project Data and do a "rerun all".

Unfortunately there is no global project language setting in the ISE
Project navigator, so you have to change the properties in each project
you create.

Have a nice simulation
eilert
 

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