Multiple components driving a single bus

Discussion in 'VHDL' started by Benjamin Couillard, Apr 22, 2009.

  1. Hi, I've got a question for you guys.

    Let's say I've got 2 blocks that can drive one bus (but there could be

    Block1 : Block
    generic map (Address => x"000")
    port map (CLK => CLK,
    ADDR => ADDR,
    RD_WR_N => RD_WR_N,

    Block2 : Block
    generic map (Address => x"004")
    port map (CLK => CLK,
    ADDR => ADDR,
    RD_WR_N => RD_WR_N,

    Let's say that when the address is not 0, DATA_OUT of block1 will be
    high-Z and when the addres is not 4 Data_out of block 2 will be high-
    Z. Will ISE synthesis engine be smart enough to realize there is no
    bus contention? Basically, will ISE infer muxes from that code? I
    realize that I could use a switch case, however I want a more scalable
    solution where I don't need to have an ugly 200-line switch case.

    I looked a Jonathan Bromley's solution too, it's very clever and it
    looks like a good solution, however I'd like to know your opinion on
    this method first. The reason, why I like the solution above is that
    the address is specified when we instantiate the block.

    Best regards.
    Benjamin Couillard, Apr 22, 2009
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  2. Benjamin Couillard


    Dec 9, 2008
    Likes Received:
    You'll need tri-state buffers (BUFT) on the DATA_OUT bus. Is there a way to 'infer' that in ISE?
    JohnDuq, Apr 22, 2009
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  3. I tried my method, and it doesn't seem to scale well. ISE seems to
    synthesize just fine even though there are address conflicts (I put
    those conflicts on purpose)

    .. I think I'm gonna use your method Jonathan, it seems to scale
    reasonably well and it avoids the mess of having one huge process
    implementing all the registers (I have about 50 register so far, but
    the number could easily double).
    Benjamin Couillard, Apr 23, 2009
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