"Non-static aggregate with multiple choices has non-static otherschoice."

Discussion in 'VHDL' started by rickman, Mar 23, 2013.

  1. rickman

    rickman Guest

    This is the code,

    Bias <= (Bias(Bias'high-1) => '1', others => '0');

    This is the error,

    "Non-static aggregate with multiple choices has non-static others choice."

    When I looked this up on the web they talk about things like using a
    loop index to select the bit in the word. Another page mentions that
    the items in an aggregate must be non-overlapping. If they need to be
    non-overlapping what is the point of the others? I could have sworn
    that I was told using others to fill in the remainder of a vector was ok
    as long as it was last in the aggregate.

    A post from 2003 used a fixed index into the vector, so it seems the
    problem is not from the use of Bias'high in the index.

    This kind of thing is what drives people nuts about VHDL. For some of
    us it is a short trip.
    rickman, Mar 23, 2013
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  2. rickman

    rickman Guest

    I'm not sure now. I had already changed the code and regenerated it for
    the post... ok, I tried changing it back and still get the error with
    the code below - copied and pasted fresh from the editor. The tool is a
    slightly old copy of Active HDL. My license is from 2008. I should try
    it with a current tool. So I tried it with AHDL 9.1 from 2011, same
    error. It also complains a bit about my coding style... picky, picky,

    Bias <= (Bias'high-1 => '1', others => '0');

    The Synplify tool... what? Oh, this code is in the test bench, so I
    can't try it under Synplify. Or more correctly Synplify complains that
    the test bench has no ports... lol

    Reading about this gets into the whole globally static vs locally static
    thing which I have to look up every time I encounter it. I like to work
    with tools that can understand at least as much as I do.
    rickman, Mar 24, 2013
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  3. rickman

    Andy Guest


    Is the range of Bias defined locally, without the use of a custom function,generic, or unconstrained port/argument index/length/range or value? If so, then it should have worked. But if Bias'range is defined based on any of the above exclusions, then bias'high (and therefore bias'high-1) is not locally static.

    There are certain parts of the VHDL language for which it is desired to allow the stand-alone analysis to determine syntactical correctness for all possible invocations of a module (entity/architecture, function, or procedure). This decision was made to make it easier to define modules (architectures, functions, prodecures) for which the syntactical correctness was not dependent upon how it was invoked or called. This in turn allows more completeverification of a module without having to test every possible invocation.While this may be irritating to individual developers of non-reusable code, it is crucial to the development of large projects with many developers/users and long, varying life-cycles.

    That said, this is a case where any NLS single element assignment is allowed, and 'others' is always allowed by itself or in addition to any assignment of LS element(s); but for some reason, 'others' cannot be used in addition to a NLS single element assignment.

    Perhaps this should be allowed in a future version of the VHDL standard (and the next version of the standard is in work now!)

    Andy, Mar 25, 2013
  4. rickman

    rickman Guest

    Thanks to everyone for your replies. I am frustrated with extremely
    arcane rationals for some of the things you can't do in VHDL. I have
    been using the language for some 18 years now, but I don't use it all
    the time. I do a project for a few weeks or months and then do some
    more VHDL a year later typically. So in some ways I am a beginner every
    time. lol I rely on cheat sheets to help me through the morass. One I
    found recently is from Hardi Electronics and was designed to make a
    pamphlet. It is organized for quick reference and has a lot more info
    than the typical single sheet info form. But it is from 2000 and only
    covers VHDL '93. Not much chance of an update as they were acquired by
    Synplicity in 2007. Oh well...


    rickman, Mar 25, 2013
  5. rickman

    KJ Guest

    Since Bias is signed, why wouldn't you just assign it like this...
    Bias <= to_signed(-2**MPCN_WIDTH, Bias'length);

    One might have also defined Bias to be an integer and assigned it like this...
    signal Bias : integer range -2**MPCN_WIDTH to (2**MPCN_WIDTH-1);
    Bias <= -2**MPCN_WIDTH;

    Since your intention appears to be that you want to assign the largest
    negative number to the value of Bias, both of these forms would seem to
    fit your intended usage better than bit picking.

    Kevin Jennings
    KJ, Mar 30, 2013
  6. rickman

    rickman Guest

    No, this is *not* the largest negative number. That would be Bias'high
    => '1'. This is supposed to be the next to highest bit set. I'm not
    sure why Bias is shown as signed. I'm not working on that code at the
    moment, but I recall the Bias parameter is supposed to be unsigned. But
    this is the test bench, maybe I made it signed here for display purposes.

    Thanks for the tip. I have been thinking of some of the conversion
    routines that let you extend the length of signed and unsigned numbers,
    but I get rusty in VHDL and forget some of this stuff.
    rickman, Mar 30, 2013
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