Hi,
I am trying to parse a file to simulate a cpu. Then, when I am parsing I identify which command (read/write from/to reg ...) and I am translating this command in VHDL..
My problem is when I want to execute a while command: The only solution that I found is to execute "loop: {...} if (..) GOTO loop" for it I have to save the line number of "loop:" and then going back to this line when I'll see "GOTO loop".
Anyone know how to do it?
Thanks.
I am trying to parse a file to simulate a cpu. Then, when I am parsing I identify which command (read/write from/to reg ...) and I am translating this command in VHDL..
My problem is when I want to execute a while command: The only solution that I found is to execute "loop: {...} if (..) GOTO loop" for it I have to save the line number of "loop:" and then going back to this line when I'll see "GOTO loop".
Anyone know how to do it?
Thanks.