Problem while doing PAR simulation.

[Srikanth]

Hi all,
I am using Xilinx 7.1 ISE . I am facing a problem while doing post
place and route simulation.
I am using model sim 6.0 version. I get the following error while doing
post place simulation
"An error occurred while executing
D:/programfiles/xilinx/data/projnav/scripts/TclFileWrapper4Halite.tcl."
Has anybody faced a similar problem or has an idea about why is it
coming?
Thanks in advance,
Srikanth

 

[Mike Treseler]

I am using Xilinx 7.1 ISE . I am facing a problem while doing post
place and route simulation.
I am using model sim 6.0 version. I get the following error while doing
post place simulation
"An error occurred while executing
D:/programfiles/xilinx/data/projnav/scripts/TclFileWrapper4Halite.tcl."
Has anybody faced a similar problem

For a synchronous design that passes
static timing and functional simulation,
there is no good reason to run a gate simulation.

If you want to run one anyway,
work from the modelsim prompt
or write your own tcl scripts.

-- Mike Treseler

 

[mk]

For a synchronous design that passes
static timing and functional simulation,
there is no good reason to run a gate simulation.

Because you said gate simulation I am assuming that you mean RTL level
for functional simulation; if so that's not entirely safe. You need to
add formal verification between rtl & gate to make sure you're
covered. Another way is to run gate level simulations without timing
(nospecify + zero delay) to at least check for the gate level
correctness for the paths you're taking in your tests (which should
have pretty good coverage anyway).