R: again on state machine

[Max]

On 10 Sep 2003 06:27:39 -0700

Your synthesizer should understand this. This assumes that
start is synchronous to clk:

process (clk, reset)
begin
if reset = '1' then
state <= st0;
elsif (clk'event and clk='1' ) then
case state is
when st0 =>
if(start ='1') then
state <= st1;
end if;
when st1 =>
state <= st2;
when st2 =>
state <= st3;
when st3 =>
state <= st0;
end case;
end if;
end process;

this work only if start goes low before st3. If start remains '1' after
st3, the machine goes in st0 and immediatly restart instead of wait the
next rising_edge(start).

thanks

 

[William Wallace]

Your homework may already be passed do, but...

Then add a st4_wait_low like st0, and modify st3. If start can be any
length (integral number of clocks) high and low, then you'll have to
take that into account, too, for st1, st2, and st3 accordingly.

when st3 =>
if (start ='0') then
state <= st0;
else
state <= st4_wait_low ;
end if;
when st4_wait_low =>
if (start ='0') then
state <= st0; -- now go wait for rising edge
end if;