reduce the CLB

[DAvid]

hello, everyone, i am a new comer here.

i would like to ask how can i reduce the usage of the CLB when coding VHDL?
cos i am using a rather old series of xilinx board(sparten s10pc84) and it
only get 196 CLB.

would anyone kindly suggest any technique to optimize the code so that less
CLB usage can be achieved?
any comments welcome
thx!!

 

[Mike Treseler]

i would like to ask how can i reduce the usage of the CLB when coding VHDL?
cos i am using a rather old series of xilinx board(sparten s10pc84) and it
only get 196 CLB.

would anyone kindly suggest any technique to optimize the code so that less
CLB usage can be achieved?

I would expect only a small improvement by optimizing code,
unless you can cut something out.

You might evaluate other synthesis tools, a newer board
or schematic entry.

-- Mike Treseler

 

[Hung]

thx

I have heard that using less assignmnet, less looping, and less variable ,
also, combine different if statement into one
will help, is it true
(it means hard-code all the thing?)