reduce the CLB

Discussion in 'VHDL' started by DAvid, Oct 24, 2004.

  1. DAvid

    DAvid Guest

    hello, everyone, i am a new comer here.

    i would like to ask how can i reduce the usage of the CLB when coding VHDL?
    cos i am using a rather old series of xilinx board(sparten s10pc84) and it
    only get 196 CLB.

    would anyone kindly suggest any technique to optimize the code so that less
    CLB usage can be achieved?
    any comments welcome
    DAvid, Oct 24, 2004
    1. Advertisements

  2. I would expect only a small improvement by optimizing code,
    unless you can cut something out.

    You might evaluate other synthesis tools, a newer board
    or schematic entry.

    -- Mike Treseler
    Mike Treseler, Oct 24, 2004
    1. Advertisements

  3. DAvid

    Hung Guest


    I have heard that using less assignmnet, less looping, and less variable ,
    also, combine different if statement into one
    will help, is it true
    (it means hard-code all the thing?)
    Hung, Oct 24, 2004
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.