(e-mail address removed) (Thomas Stanka) wrote:
[shorted to a line]
What option forces synthesis to keep the 'NOT NOT A' delay?
And, are all these statements under the same process()?
First I don't mean to insult you in any way.
If you can't answer this questions by your self, your IMHO not
experienced enough for doing asynchronous design in its real meaning.
Please start doing synchronos designs, you will likely fail getting
your synthesis tools doing the right thing in an asynchronous design,
if you even can't figure out how to instantiate two inverter. I never
done a real asynchronous design for myself and I'm not sure if I ever
want to because of the mass of problems I expect to encounter.
What option forces synthesis to keep the 'NOT NOT A' delay?
There are several ways forcing your synthesis tool keeping two
inverter, depending on which tool you are using.
Independent of your tool you could instantiate two inverter directly
from the vendor library and forbid your tool to systhesise these
libraryelments.
Or you could instantiate one inverter and manipulate the netlist after
synthesis, inserting a second.
But your tool will likely offer you one or two easier ways *g*.
And, are all these statements under the same process()?
They are all out of a process (concurrent statement), but there is no
problem
putting the lines in one process or split them over more processes.
bye Thomas