Send a PULSE on input change, asynchronous

Discussion in 'VHDL' started by Jamie, Oct 20, 2003.

  1. Jamie

    Jamie Guest

    Trying to formulate and asynchronous design again. I need to generate
    a low pulse to signal an IRQ and wake-up a microcontroller.

    My conditions.

    port(A, B, RIGHT, ENTER: in std_logic; PULSE: out std_logic;)

    1. on A and B any change should send a pulse.
    2. ENTER and RIGHT only a high-to-low (falling_edge) should send a

    Any suggestions on this?
    Jamie, Oct 20, 2003
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  2. There are a few problems concerning the width of the pulses, racing
    conditions and so on. But in general I would use a simple xor to
    detect changes.
    First you have to delay each input to get a chance to see changing

    A_Delayed<=NOT NOT A; -- Force synthesis to keep this delay

    Pulse_A<=A_delayed XOR A;
    Pulse_Enter<=(Enter_delayed XOR Enter) AND NOT Enter;-- falling Edge

    Pulse<=Pulse_A OR .. OR Pulse_Enter;

    bye Thomas
    Thomas Stanka, Oct 21, 2003
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  3. Jamie

    Jamie Guest

    What option forces synthesis to keep the 'NOT NOT A' delay?

    And, are all these statements under the same process()?

    Jamie, Oct 21, 2003
  4. Consider a synchronous process.

    If this is out of the question, then consider
    an HC14 and some diodes, caps, and resistors.
    At least you can tune up the delays that way.

    -- Mike Treseler
    Mike Treseler, Oct 21, 2003
  5. [shorted to a line]
    First I don't mean to insult you in any way.
    If you can't answer this questions by your self, your IMHO not
    experienced enough for doing asynchronous design in its real meaning.
    Please start doing synchronos designs, you will likely fail getting
    your synthesis tools doing the right thing in an asynchronous design,
    if you even can't figure out how to instantiate two inverter. I never
    done a real asynchronous design for myself and I'm not sure if I ever
    want to because of the mass of problems I expect to encounter.
    There are several ways forcing your synthesis tool keeping two
    inverter, depending on which tool you are using.
    Independent of your tool you could instantiate two inverter directly
    from the vendor library and forbid your tool to systhesise these
    Or you could instantiate one inverter and manipulate the netlist after
    synthesis, inserting a second.
    But your tool will likely offer you one or two easier ways *g*.
    They are all out of a process (concurrent statement), but there is no
    putting the lines in one process or split them over more processes.

    bye Thomas
    Thomas Stanka, Oct 22, 2003
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