SYNTHESIS QUESTIONS

[Bar Nash]

Hi all

I have several questions about synthesis :

1> In case that the gate level model reacts differently to the test bench
then the RTL model what is to be done ?

2> Is the gate level model tecnology specific or only at the place and route
the model becomes technology specific ?

Thanks
EC

 

[Mike Treseler]

1> In case that the gate level model reacts differently to the test bench
then the RTL model what is to be done ?

Edit synthesis and/or testbench code and try again.

2> Is the gate level model technology specific

Yes.

Note that many designers use STA instead of gate level sims.
See also:
http://groups.google.com/groups/search?q="simulation+works"++pitfalls

-- Mike Treseler

 

[KJ]

Hi all

I have several questions about synthesis :

1> In case that the gate level model reacts differently to the test bench
then the RTL model what is to be done ?

Most likely the testbench signals are not setup properly relative to the
clock and you're violating the setup and/or hold time of the final design.
In short, your testbench is not modelling the reality that will be needed to
get your actual design to work.

KJ

 

[Bar Nash]

MIKE
What is STA exactly ?

EC

Edit synthesis and/or testbench code and try again.

Yes.

Note that many designers use STA instead of gate level sims.
See also:
http://groups.google.com/groups/search?q="simulation+works"++pitfalls

-- Mike Treseler

 

[Muzaffer Kal]

MIKE
What is STA exactly ?

Static Timing Analysis. If you have a fully synchronous design,
correctly constrained, then you don't need back-annotated gate-level
simulations assuming your RTL sims and STA pass [and you're sure that
synthesizer didn't make a mistake which can also be proven formally.]

Muzaffer Kal
http://www.dspia.com

 

[Tricky]

I have several questions about synthesis :

1> In case that the gate level model reacts differently to the test bench
then the RTL model what is to be done ?

This will often happen when you dont follow standard templates for
processes or you forget to put signals inside a sensitivity list. When
signals are missed from the list, the simulator wont simulate
correctly, but the synthesiser will create whatever you wrote, because
it doesnt care about the sensitivy lists, though most synthezisors
should warn you that signals are missing from the list.

 

[Mike Treseler]

*I understand that the Static Timing Analysys is done on the Gate Level
model that is NOT technology spesific , just the gate level *
*representation of the RTL model genenerated by the synthesis tool .*
*Am I right ? *

No. It's about the routed delays of the technology netlist.
Nothing to do with the HDL.

-- Mike Treseler

 

[Andy]

Static Timing Analysis. If you have a fully synchronous design,
correctly constrained, then you don't need back-annotated gate-level
simulations assuming your RTL sims and STA pass [and you're sure that
synthesizer didn't make a mistake which can also be proven formally.]

And you're sure that any multi-cycle or false path constraints are
correct and accurately specified, etc.(you don't want STA to think a
specified path is multi-cycle if it is really single-cycle).

Andy