LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.MATH_REAL.ALL; -- This contains the SIN( )
ENTITY Min_TestBench_Sampler1_vhd IS
Port ( CLKX: out STD_LOGIC;
Dataout : inout STD_LOGIC_VECTOR (7 downto 0));
END Min_TestBench_Sampler1_vhd;
ARCHITECTURE behavior OF Min_TestBench_Sampler1_vhd IS
---------------------- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sampler_version1
PORT( Master_Clk : IN std_logic;
Datin : IN std_logic_vector(7 downto 0);
Datout : OUT std_logic_vector(7 downto 0);
Clks : OUT std_logic );
END COMPONENT;
-------------------------------------------------------------------- Inputs
SIGNAL Master_Clk : std_logic := '0';
SIGNAL Datin : std_logic_vector(7 downto 0) := (others=>'0');
-------------------------------------------------------------------- Outputs
SIGNAL Datout : std_logic_vector(7 downto 0);
SIGNAL Clks : std_logic;
-----------------------------------------------------------------------------
signal Clk_v1: STD_LOGIC := '0';
-- Please note - Shared variables can be used for interprocess data
-- exchange. Moreover can they be observed under a simulation as well
shared variable Delta_step: real := 100.0;
shared variable Delta: real := 1000.0;
shared variable Delta_xx: real := -1.0;
BEGIN
-- --------------------------------- Instantiate the Unit Under Test (UUT)
UUT: Sampler_version1 PORT MAP( Master_Clk => Master_Clk,
Datin => Datin,
Datout => Datout,
Clks => Clks );
Master_Clk <= not Master_Clk after 5 ns; -- 100 MHz master clock
Datin <= DataOut;
CLKX <= Clk_v1;
------------------------------------------------------------------------
-- This process creates a clk-signal with a variable frequency
-- not use if its useful in practice, but it demonstrates what can
-- be done.
-- The shared variable "Delta" will decrease with the value "Delta_step"
-- for each step will the "Delta_step" value change with "Delta_xx"
------------------------------------------------------------------------
Clk_generator: process
begin
Clk_v1 <= not Clk_v1; -- Toogle the Clk
Delta := 1000.0; -- Ready for a new count down
while Delta>0.0 loop -- while not done
wait for 10 ps; -- adjust this if needed
Delta := Delta - Delta_step; -- one step down
end loop;
if Delta_xx < 0.0 then
if Delta_step < 2.0 then
Delta_xx := 0.1;
end if;
else
if Delta_step > 198.0 then
Delta_xx := -0.1;
end if;
end if;
Delta_Step := Delta_step + Delta_xx;
end process Clk_generator;
--------------------------------------------------------------------
-- This process driven by an external clock signal
-- the statement "wait until rising_edge( clk_v1)" do the trick
--------------------------------------------------------------------
Sinus_generator: process
constant Umax: integer := 127; -- Max amplitude
constant f: real := 2.0E6; -- Frequency [Hz]
constant Tper: real := 1.0/f; -- Period of fr.
-- If you can find a way to convert real to time please let me know
constant Delta: real := 1000.0E-12; -- delta time - sec
constant DeltaWait: time := 1000 ps; -- delta time - ps
--------------------------------------------------------------------
variable t: Real := 0.0; -- Actual time
variable angle: real := 0.0; -- Actual angle in radians
variable Usin: real := 0.0; -- The sin value [real]
variable Usin_int: integer; -- The sin value as integer
begin
wait until rising_edge( Clk_v1);
angle := 2.0 * MATH_PI * t * f; -- calculate angle
t := t + Delta; -- next time
Usin := real(Umax)*( SIN( angle)+1.0); -- Usin calculation
Usin_int := integer(Usin); -- convert real to integer
Dataout <= conv_std_logic_vector( Usin_int, 8); -- to vector
end process sinus_generator;
--------------------------------------- not in use -----------------
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
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