J
Jim Lewis
Date: Thursday, July 18, 2013
OSVVM Europe Session, 3-4 PM CEST (6-7 AM PDT) http://www.aldec.com/en/events/303
OSVVM US Session, 11 am - 12 Noon PDT http://www.aldec.com/en/events/302
Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OS-VVM Chief Architect
Abstract:
At the lowest level, Open Source VHDL Verification Methodology (OSVVM), is a set of packages that provide concise and powerful methods to implement functional coverage and randomization. OS-VVM uses these packages to create an intelligent testbench methodology that allows mixing of "Intelligent Coverage™" with directed, algorithmic, file based, or constrained random testapproaches. Having an intelligent testbench approach built into the coverage modeling puts OS-VVM a step ahead of other verification methodologies, such as SystemVerilog and UVM.
Attend this webinar and learn how to utilize OSVVM to add functional coverage, Intelligent Coverage, and constrained random methods to your current testbench.
Agenda:
What and Why OSVVM, Functional Coverage, and Randomization
Writing Item (Point Coverage)
Writing Cross Coverage
Constrained Random is 5X or More Slower
Intelligent Coverage
OS-VVM is More Capable
Additional Randomization in OS-VVM
Weighted Intelligent Coverage
Coverage Closure
OS-VVM Loves any Testbench
Additional Methods for Verification
Benefits of OSVVM include:
Faster Test Construction, focus is on functional coverage
Faster simulations: O(Log N) faster than constrained random and no solver.
Goes beyond other verification languages (SystemVerilog and 'e')
Works with your current VHDL testbench
Uses entity and architectures for structure (just like RTL).
Is language accessible. Able to refine with code.
Readable by ALL (Verification and RTL engineers).
OSVVM is open-source package based. It compiles under VHDL-2008 or VHDL-2002(with minor adaptations), so you can use it today. See http://osvvm.org
OSVVM Europe Session, 3-4 PM CEST (6-7 AM PDT) http://www.aldec.com/en/events/303
OSVVM US Session, 11 am - 12 Noon PDT http://www.aldec.com/en/events/302
Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OS-VVM Chief Architect
Abstract:
At the lowest level, Open Source VHDL Verification Methodology (OSVVM), is a set of packages that provide concise and powerful methods to implement functional coverage and randomization. OS-VVM uses these packages to create an intelligent testbench methodology that allows mixing of "Intelligent Coverage™" with directed, algorithmic, file based, or constrained random testapproaches. Having an intelligent testbench approach built into the coverage modeling puts OS-VVM a step ahead of other verification methodologies, such as SystemVerilog and UVM.
Attend this webinar and learn how to utilize OSVVM to add functional coverage, Intelligent Coverage, and constrained random methods to your current testbench.
Agenda:
What and Why OSVVM, Functional Coverage, and Randomization
Writing Item (Point Coverage)
Writing Cross Coverage
Constrained Random is 5X or More Slower
Intelligent Coverage
OS-VVM is More Capable
Additional Randomization in OS-VVM
Weighted Intelligent Coverage
Coverage Closure
OS-VVM Loves any Testbench
Additional Methods for Verification
Benefits of OSVVM include:
Faster Test Construction, focus is on functional coverage
Faster simulations: O(Log N) faster than constrained random and no solver.
Goes beyond other verification languages (SystemVerilog and 'e')
Works with your current VHDL testbench
Uses entity and architectures for structure (just like RTL).
Is language accessible. Able to refine with code.
Readable by ALL (Verification and RTL engineers).
OSVVM is open-source package based. It compiles under VHDL-2008 or VHDL-2002(with minor adaptations), so you can use it today. See http://osvvm.org