The corresponding Actel library of the Xilinx UNISIM

[bs.addr]

Hi to All;

I am very new in VHDL programming and implementation. I am
synthetising a program with the UNISIM library in Xilinx environment.
In the library, I needed the components: FDC, LDC, RDC, ... so on. But
I would like now to use ACTEL Modelsim for which I don't know the
corresponding library name.

Can anyone please tell me how to get the corresponding library for
Actel modelsim "Libero".

Thanks in advance.

 

[Mike Treseler]

I am very new in VHDL programming and implementation. I am
synthetising a program with the UNISIM library in Xilinx environment.
In the library, I needed the components: FDC, LDC, RDC, ... so on. But
I would like now to use ACTEL Modelsim for which I don't know the
corresponding library name.

If you are changing devices from Xilinx to Actel,
the vendor specific components and magic words won't work.
Better to write and simulate your own generic vhdl code
and use vendor tools for synthesis only.


-- Mike Treseler

 

[D Stanford]

I am very new in VHDL programming and implementation. I am

synthetising a program with the UNISIM library in Xilinx environment.
In the library, I needed the components: FDC, LDC, RDC, ... so on. But
I would like now to use ACTEL Modelsim for which I don't know the
corresponding library name.

Can anyone please tell me how to get the corresponding library for
Actel modelsim "Libero".

If you are doing a design targeted for an Actel chip, you will want to
use Actel libraries, such as the apa (actel pro asic) library instead
of Xilinx libraries intended for use with Xilinx chips. You're Actel
tools should have these libraries in both precompiled and vhdl formats.

 

[Thomas Stanka]

Hi,

I am very new in VHDL programming and implementation. I am
synthetising a program with the UNISIM library in Xilinx environment.
In the library, I needed the components: FDC, LDC, RDC, ... so on. But
I would like now to use ACTEL Modelsim for which I don't know the
corresponding library name.

These library elements are primitive gates, which should only occure in
your netlist, not in your RTL-Code. Take your RTL-Code and synthesise
it with Synplicity for Actel technology, after layout with designer you
can get a VHDL-netlist with only Actel primitives. The library name
depends on your target technology (apa, ax, a54sxa, ...), as Actel has
no unique library name for all technologies.

If you have primitves in your RTL-Code, you need to identify their
functionality and replace them with gates with similiar functionality
(eg. FDC with DF1).
If you use Xilinx macros you should use ActGen to create similiar
macros for Actel.

Can anyone please tell me how to get the corresponding library for
Actel modelsim "Libero".

From the Libero CD.

bye Thomas