Unresolved reference message

Discussion in 'VHDL' started by hemant.bhargava7, Dec 20, 2012.

  1. In hierarchical netlist, I have top module name as "r_abc" and inside that module is a flop as:

    (hierarchical names)
    ( .C ( clk )
    .D ( I0 )
    .CE ( CE_pin )
    .Q ( Output_pin ) );

    So, when i try to access the CE pin of this flop in my testbench, i get "Unresolved reference" error. I did it as:
    r_abc.\abc/def/ghi/jkl .CE
    <top_module>.<flop_name> .CE

    Can someone figure out what is going wrong here?

    - Hemant
    hemant.bhargava7, Dec 20, 2012
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  2. hemant.bhargava7

    Rob Gaddi Guest

    On Thu, 20 Dec 2012 09:00:31 -0800 (PST)
    Offhand, I'd say the problem is that you're writing Verilog. You do
    know that this is comp.lang.vhdl, right? With a VHDL in it.

    Not that someone here isn't likely to have spillover knowledge that can
    help you out, but so far you've failed at appropriate question
    targeting, and might want to repost it somewhere better suited. There
    is a comp.lang.verilog, though having never stuck my head in I can't
    tell you whether or not it's particularly active.
    Rob Gaddi, Dec 20, 2012
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