hello,
can anybody help me out for generating vcd file in ncverilog?
I have generated that file in verilog code using $dumpfile(myfile.vcd"). Also I have added required $dumpvars, $dumpon, $dumpoff statements. But not able to see the variables in the vcd file. How can I get those veriables in my vcd file? which command is used to simulate and to get timing windows in this tool? I am using < ut & command and able to open the waveform window but not able to get signals in the waveform.
Regards,
Sneha
can anybody help me out for generating vcd file in ncverilog?
I have generated that file in verilog code using $dumpfile(myfile.vcd"). Also I have added required $dumpvars, $dumpon, $dumpoff statements. But not able to see the variables in the vcd file. How can I get those veriables in my vcd file? which command is used to simulate and to get timing windows in this tool? I am using < ut & command and able to open the waveform window but not able to get signals in the waveform.
Regards,
Sneha