vhdl 101

[martstev]

I am fairly new at VHDL...have two questions:

1) any recommended books with loads of exampls - VHDL and digital
logic.(I know there is so much FREE on the web, but I want to start
with fundamentals)

2) any suggestion about how can i code following timing signals in VHDL

thanks in adavance

this is what want to do...
based on my inputs, I want to generate some timing signals..
for examples: if my input (4bit wide) is "0001", I need to create a
10uS pulse (T1) avery 1ms and want to created another pulse (18us wide)
2uS after the leading edge of T1



_______ _______
| | | |
| 10us | | 10us |
T1 | | | |
________________| |________________________| |_________________
|<-------------- 1ms -------------->

__________ __________
2us---->| |<---- | | |
| | | |
T2 | 18us | | 18us |
__________________| |________________________| |_______


thx,
MARTIN

 

[Andrew FPGA]

Do you want to generate T1/T2 in a simulator or in real FPGA hardware?
If simulation you can do things like "wait for 10 us;". If the target
is FPGA hardware then you must use vhdl constructs that are
synthesizable ( wait for xx us is not). The FPGA hardware should have a
clock signal. Use counters that count clock ticks to generate whatever
delays you would like.

E.g. say you have a 10MHz clock source. To generate a pulse 1 us long
you need to count for 10 clock cycles.

 

[martstev]

Thank you Andrew for your reply!
Yeah..I need this for the FPGA hardware. So I suppose I have to
implement counters to generate T1 and T2. is that a true statement??

Martin

 

[Colin Paul Gloster]

On Sun, 13 Aug 2006 (e-mail address removed) wrote:

"[..]
this is what want to do...
based on my inputs, I want to generate some timing signals..
for examples: if my input (4bit wide) is "0001", I need to create a
10uS pulse (T1) avery 1ms [..]



_______ _______
| | | |
| 10us | | 10us |
T1 | | | |
________________| |________________________| |_________________
|<-------------- 1ms -------------->

[..]"

The quoted text and the diagram do not correspond to each other: if
something happens every 1ms then the period of 1ms should not be measured
from the rising edge of one pulse to the falling edge of another pulse.

 

[willie]

A good book on VHDL and Verilog, it covers both, is
HDL Programming Fundamentals VHDL and Verilog
by Nazieh M. Botros
ISBN 1-58450-855-8