VHDL vs. System Generator, et al.

[Robert G. Kaimer Jr.]

I've been working with VHDL for several years. Recently, a DSP-intensive
portion of one of our designs was developed by our Sr. Scientist using
Simulink and System Generator. He didn't have any previous FPGA
experience, and has since presented what is widely considered a
convincing argument for the eventual replacement of VHDL hand coding at
our company.

I realize that System Generator is geared toward DSP (and that it
generates VHDL code), but is there any weight to the argument that it
can replace coding of VHDL (or Verilog) outright? Is there some aspect
of HDLs (or deficiency of system-oriented tools) that makes developing
coding proficiency worthwhile?

Thanks/Regards,
Bob

 

[Paul Uiterlinden]

I've been working with VHDL for several years. Recently, a
DSP-intensive portion of one of our designs was developed by our Sr.
Scientist using Simulink and System Generator. He didn't have any
previous FPGA experience, and has since presented what is widely
considered a convincing argument for the eventual replacement of
VHDL hand coding at our company.

Coincidentally, I happened to read this article today:
http://www.fpgajournal.com/articles_2006/20061128_dsp.htm

Further than that, I do not have a real opinion on the subject
(lacking experience in DSP and MatLab).

Of course, there is a tendency to higher levels. After all, drawing
gates and schematics have been replaced almost entirely by writing
VHDL/Verilog.

 

[jez-smith]

Coincidentally, I happened to read this article today:
http://www.fpgajournal.com/articles_2006/20061128_dsp.htm

Further than that, I do not have a real opinion on the subject
(lacking experience in DSP and MatLab).

Of course, there is a tendency to higher levels. After all, drawing
gates and schematics have been replaced almost entirely by writing
VHDL/Verilog.

My experiance with these sorts of automated system generators is that
they are pretty dreadful and there is little to commend them, its very
similar to the idea that you can generate good hardware by using C or C
with parrelel processing extensions which was a popular idea a few
years ago and has nw dies a death although it keeps on cropping up
again amongst software types who dont really understand hardware.

 

[Andy]

Algorithmic portions of the design (i..e the DSP part) are, or can be,
handled pretty well by various higher level design environments, such
as System Generator, Catapult, etc.

Where most of these environments fall down is in the interfaces to get
data into and out of the FPGA. For popular, standard interfaces,
there's IP; for everything else, there's HDL coding.

Andy

 

[Thomas Stanka]

Hi,

I realize that System Generator is geared toward DSP (and that it
generates VHDL code), but is there any weight to the argument that it
can replace coding of VHDL (or Verilog) outright? Is there some aspect
of HDLs (or deficiency of system-oriented tools) that makes developing
coding proficiency worthwhile?

Code generators are not new, they get only (significant?) better.

Code Generators are allways restricted in producing your code. There's
in principle no difference between a code generator for a multiplier or
a codegenerator for complex DSP. You always get fast code, but you
lack control over the code. The less inputs your tool nedds, the less
control is possible.

A code generator is good, if you have less contraints, but is unusable
if the generated code didn't match your timing, area, power budget,....
The increasing usage of IPs is a fact and increasing usage of (simple)
code generators are also a fact. But there will be ever designs or
parts of designs, where you need to build your own code to meet your
constraints.

bye Thomas

 

[Martin Thompson]

Coincidentally, I happened to read this article today:
http://www.fpgajournal.com/articles_2006/20061128_dsp.htm

Further than that, I do not have a real opinion on the subject
(lacking experience in DSP and MatLab).

Of course, there is a tendency to higher levels. After all, drawing
gates and schematics have been replaced almost entirely by writing
VHDL/Verilog.

Except that Sysgen *is* pretty much low-level unless you can make use of
the predefined high level blocks (which are very commsy). For our
application, it was *just* like writing VHDL - you have to instantiate
registers, adders and the like and wire them up. Just like the old
schematic days

Pros:
* It understands fixed point, so it lines the decimal points up for you
and propogates the size of results.
* You get all of Simulink's interesting signal sources for free
If you already know Simulink, it's easier than learning VHDL. You'll
still have to learn FPGA though

Cons:
* Not that different to hand coded VHDL, unless you want a Viterbi
decoder or the like.
* You get all of Simulink's "features" - like it has no idea of
hierarchy in a model unless you start removing bit and creating
libraries. Makes testbenches a pain.
* It takes ages to run and then says "you've got too many bits going
into this register" before dying. You had to wait about 3 mins on our
design (which was not *that* big, a middling Virtex-II) to get these
errors, and eventually it would synthesise. Which also took ages!

Cheers,
Martin

 

[Jahagirdar Vijayvithal S]

My experiance with these sorts of automated system generators is that
they are pretty dreadful and there is little to commend them, its very
similar to the idea that you can generate good hardware by using C or C
with parrelel processing extensions which was a popular idea a few
years ago and has nw dies a death although it keeps on cropping up
again amongst software types who dont really understand hardware.

As system complexity increases we arrive at a point where we have to
make a tradeoff between getting the most optimised design and managing
design complexity. The software industry went through a similar stage
where it moved from assembly to c to java where it traded off compact
code and faster run time for managable designs. Afterall today processor
cycles and memory is cheap.

The digital design sector has similarly moved from hand crafting each
gate(full custom design) to inferring standard gates from RTL (ASIC).
Quite a few people would today argue that gates are cheap

The current RTL languages were designed to handle complexity of the 80's.
Recent extensions to the languages focus more on the verification aspect
rather than correct by construction(RTL coding).

While simulink or the current crop of C++ based synthesis tools may or may not
be the solution. The need for next generation hardware design languages
certainly exists.

Regards
Jahagirdar Vijayvithal S

 

[ajjc]

Bob,
FYI, check out the following report:

Daresbury Report:
http://www.cse.clrc.ac.uk/disco/publications/FPGA_overview.pdf

alan

 

[boysr2003]

Comment on VHDL vs. System Generator

Hi,
my name is Yassir Boukhriss, from my experience, System Generator is not intended to replace VHDL coding. It's a convenient tool to generate VHDL code if you can match the timing constraints of your design. What you can do is use system generator and write vhdl code. Sometimes it's easier to implement something in system generator than writing its vhdl code. For example it's easier to implement a phase locked loop in system generator than writing its vhdl code. To meet timing constraints in system generator, you need to adjust the parameters in the system generator token to match the constraints of your design. Again, in some cases system generator is not useful.
Take care.

 

[se]

As system complexity increases we arrive at a point where we have to
make a tradeoff between getting the most optimised design and managing
design complexity. The software industry went through a similar stage
where it moved from assembly to c to java where it traded off compact
code and faster run time for managable designs. Afterall today processor
cycles and memory is cheap.

We evaluated several such tools a couple of years ago and have been
using Simulink since. We typically have an algorithmist use Simulink
and the traditional FPGA developer works the rest of the design.

Sam

 

[redpathdu]

Not all are bad...there are some good ones out there. Though not
supporting Matlab, the VHDL code produced by Tyd-IP code Generator is
first rate.

Regards
Duncan

 

[Colin Paul Gloster]

Jez Smith posted on 29 Nov 2006 13:49:31 -0800:

"[..] very
similar to the idea that you can generate good hardware by using C or C
with parrelel processing extensions which was a popular idea a few
years ago and has nw dies a death although it keeps on cropping up
again amongst software types who dont really understand hardware."

I have noticed many such attempts. The earliest I have found so far is
one which apparently existed in 1985 called CDL (C-Development
Language and later Chip Design Language and CDLsuperscript:TM) (not to
be confused with CDL (Computer Design Language). Is any one aware of
any earlier attempts?

Regards,
Colin Paul Gloster

 

[ngcolin]

Sysgen vs Coregen vs HDL

Sysgen is really a super Coregen, and have its pro and con, vs Coregen.

Sysgen cannot deal with more than one clock domain, that restricted what it can do in a complex design. It also can't include a HDL module.

So, the workable practice is use Sysgen like a super coregent, and generate HDL block to be included in a HDL wrapper and other HDL modules.

Places that use mostly Sysgen are due they did not get a handle on HDL.