Visibility rules

[Paul Uiterlinden]

I am curious how simulators deal with code as shown below when analyzing it:

PACKAGE pkg IS
FUNCTION min
(
a : integer;
b : integer
) RETURN integer;
END PACKAGE pkg;

PACKAGE BODY pkg IS
FUNCTION min
(
a : integer;
b : integer
) RETURN integer IS
BEGIN
IF a < b THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION min;
END PACKAGE BODY pkg;

ENTITY ent IS
END ENTITY ent;

USE work.pkg.ALL;

ARCHITECTURE arch OF ent IS
BEGIN
p: PROCESS IS
VARIABLE v : integer;
BEGIN
v := min(123, 456);
WAIT;
END PROCESS p;
END ARCHITECTURE arch;

I use ModelSim. Up to version 10.0 (including 10.0beta1) this used to work
fine. Version 10.0a (and I suppose 10.0 as well) now complains:

** Error: vhdl/function_min.vhd(34): (vcom-1078) Identifier "min" is not
directly visible.
Potentially visible declarations are:
std.STANDARD.min (physical unit)
work.pkg.min (function)

So clearly there is a collision now with the physical unit "min" from type
TIME.

Technote MG539708 by Mentor explains that the above behaviour is LRM
compliant. The fact that this used to work in earlier versions is an
unlucky event, based on the order in which declarations were found (USE
clauses). The clause "USE std.standard.all" always is present implicitly.

So, could somebody please analyze the above code in a different simulator to
see if it is accepted or not?

Additionally, I wonder why a function name "DEL" (instead of "min) *is*
accepted. DEL is one of the enumeration literals of type CHARACTER.

To add to the fun: this is not accepted by any version of ModelSim:

PACKAGE pkg IS
COMPONENT del IS
END COMPONENT del;
END PACKAGE pkg;

ENTITY ent IS
END ENTITY ent;

USE work.pkg.ALL;

ARCHITECTURE arch OF ent IS
BEGIN
del_i: del;
END ARCHITECTURE arch;

Ah, wait a minute: the clarification of error message 1078 explains why del
can be used as function and not as a component (both declared in a
package):

vcom Message # 1078:
The name is ambiguous according to the visibility rules.
IEEE Std 1076-1993, 10.4 Use clauses, line 234:
Potentially visible declarations that have the same designator are not
made directly visible unless each of them is either an enumeration
literal specification or the declaration of a subprogram (either by a
subprogram declaration or by an implicit declaration).

Still, I am curious if my code with function min fails in other simulators.

 

[Paul Uiterlinden]

It fails in Cadence:

ncvhdl -v93 test.vhd
ncvhdl: 10.20-s009: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
v := min(123, 456);
|
ncvhdl_p: *E,IDENRD (test.vhd,34|13): identifier (MIN) is not visible,
as it is directly visible via use clauses from more than one design
unit. This results in conflict. This object is defined at:
STD.STANDARD
WORKLIB.PKG

Thanks. That is the correct answer (LRM-wise). If only ModelSim would have
given that answer years ago. Now I'm stuck with many many VHDL files that
are not LRM compliant.

I was happy when I read that in VHDL-2008 the functions minimum and maximum
where added, instead of min and max. Those function names where already in
use by me. Now I now that min was a bad choice anyway.