When others case and Synthesis

Discussion in 'VHDL' started by Luca D., Mar 5, 2010.

  1. Luca D.

    Luca D.

    Joined:
    Mar 5, 2010
    Messages:
    1
    Likes Received:
    0
    Hi all!
    I've just started to study how the synthesis process works and can't find any information about what happens when values different from '1' and '0' are used for a std_logic signal.
    For example, given the following code:
    Code (Text):

    case x is
      when '1' => y <= '0';
      when '0' => y <= '1';
      when others => y <= 'X';
     
    How would the circuit be synthesised?
    And which will be the difference if in the last line y gets assigned 'Z' or '-'?

    Thank you so much!
    Bye
     
    Luca D., Mar 5, 2010
    #1
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.