Xilinx memories

Discussion in 'VHDL' started by Marc Jeambrun, Aug 3, 2006.

  1. Hello,

    Does anyone know if there exists a Xilinx block memory IP core for FPGA
    synthesis that includes an acknowlegment signal ACK ???

    Thanks in advance.

    Marc Jeambrun, Aug 3, 2006
    1. Advertisements

  2. Marc Jeambrun

    Mark Norton Guest

    Just fired up coregen. The block memory FIFO has write acknowledge.
    The single port block RAM has an option for "handshaking signals". I
    haven't looked up the datasheet for the SPBRAM but it sounds like what
    you are looking for.

    Best regards,
    Mark Norton, Aug 4, 2006
    1. Advertisements

  3. Thanks Mark for the write-ACK signal concerning the FIFO block memory.

    In fact, I've already checked out "handshaking signals" on Xilinx single
    port memories and it seems quite insufficient for acknowledging a read
    or write access. For instance, according to the official support, "Ready
    for DATA (RFD) is always true, except when EN is inactive" !!!!

    I'm on my way to find out an alternative to this lack in the Xilinx model.


    Mark Norton a écrit :
    Marc Jeambrun, Aug 4, 2006
  4. Marc Jeambrun

    Eric Smith Guest

    It's a single-cycle synchronous RAM. Every cycle that it is enabled,
    it performs a read or write, and completes it that cycle. So the behavior
    they spec for RFD is the only behavior that makes much sense.

    If you want to pretend that the RAM is slower than single-clock, you could
    add a register to delay the ACK by a cycle.
    Eric Smith, Aug 14, 2006
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.