Xistinks

[gzidude]

Is there some some ridiculously small project size limit or some other limiting factor that will cause Xilinx ISE (both v6 and v10) to tell me that everything is perfectly fine, when it, according to the RTL generated schematic, decides not to connect a particular wire to its destination? No matter how many times I restart the whole project, it continues to not internally wire the same signal to any of its destinations AND it doesn't bother to tell me about it or give hint as to why. No error messages show up, nothing. The only thing I'm doing that I've never done before is using a schematic on the top of my hierarchy.