code simulates great, but error in synthesis

Discussion in 'VHDL' started by digital pig, Oct 27, 2007.

  1. digital pig

    digital pig

    Joined:
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    . . . . . . . . . .
     
    Last edited: Nov 9, 2007
    digital pig, Oct 27, 2007
    #1
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  2. digital pig

    scottcarl

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    May 4, 2007
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    D-Pig,
    Did you check your timing report for errors, synthesis warnings, or tearing out of unused logic? Did you actually set the clock and timing constraints correctly for your design? Are you crossing clock domains somewhere? Is your input identical to that being used in simulation? Did you set some unnecessary place & route constraints where none were needed? Did you run a post place & route timing simulation of the design? Sometimes the design is so large that this is totally impractical. You can also run a post-synthesis (with the .edf file) on your design to make sure the synthesizer didn't rip some logic out.

    There are a multitude of issues that can cause things to not work in lab even when simulation looks good. This is what makes someone a true hardware engineer, not just a coder. I would either suggest posting you vhdl here or ask someone to review your simulation with you and place & routing with you.

    Later,
    Scott C
     
    scottcarl, Nov 5, 2007
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