doubling clock frequncy

Discussion in 'VHDL' started by bxbxb3, Dec 19, 2004.

  1. bxbxb3

    bxbxb3 Guest

    about clock doubling, one of my friend neil says:
    "No really easy way, look at the specification of your device. Most of the
    bigger have DLLs. if your have, use it.
    Way back, when no devices had DLLs, we used a rather crude trick. You feed
    the clock to one toggling DFF and also to another DFF via a lot of
    instantiated inverters/buffers (to get a lot of delay). XOR the outputs
    and you will get a pulse at the clock edge (the width will be the amount
    of delay you have been able to introduce). Then we made another copy of
    the logic, but with an inverted clock. XORing together the resulting
    signals gave a short pulse at both rising and falling clock edge.That
    meant we had actually doubled the clock frequency, but usually it
    was of little use, since the clock was not nearly symmetrical. The fix for
    that was to do it all over again and divide the resulting clock by two to
    get it symmetrical.

    Worked only for relatively slow clocks since the process used had to be
    able to cope with twice the frequency we needed.I do not recommend you to
    try this, it is just that I have filed it under the tab "meaningless
    knowledge" and I do not seem to be able to scrub it (the tab) completeatly
    clean. But, if you can not find another help you can try it.

    When we used it, synthesis tools where not so advanced so they usually did
    what they where told. Nowadays I guess it would be a lot of problems (if
    possible) to get any of them not to optimize away the extra delay
    bxbxb3, Dec 19, 2004
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