Paul Uiterlinden said:
By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These
two latches form a so called master-slave pair.
That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.
I think someone didn't read carefully before posting. The master/slave
flip flop does implement the edge triggered logic.
Quoting from "The Art of Digital Design" by Prosser and Winkel,
Second Edition, Chapter 4:
The master-slave flip-flop appears to be an attractive edge-driven
device. Why are we not content with this design? Because the
master flip-flop is still a 1's catcher during the positive half
of the clock cycle. This means that R and S must stabilize during
the negative half of the clock, since the master flip-flop will
react to any T glitches during the positive clock phase. We could
greatly simplify our digital circuit designs if we could eliminate
the 1's-catching behavior. We need a flip-flop that samples its
inputs only on a clock edge and changes its outputs only as the
result of the clock edge. Such a device is called a <i>pure edge-
driven flip-flop</i>.
Unfortunately the authors do not explain the construction of such
a device, though the 7474 and 74109 are real-world examples of it.
Metastability is not explained until Chapter 12.
The 7474 is a slightly tricky master-slave circuit.
The 7474 is not a master-slave flip-flop. It actually contains three
S-R flip-flops in a non-obvious configuration, very much unlike what
Paul Uiterlinden described.