FIR test ?

Discussion in 'VHDL' started by Bar Nash, Oct 12, 2008.

  1. Bar Nash

    Bar Nash Guest

    Hi all

    How a FIR model is tested after verification and synthesys ?

    I mean how do we know that the FIR will have the expected frequency
    response when put on silicon ?

    Thanks
    EC
     
    Bar Nash, Oct 12, 2008
    #1
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  2. Bar Nash

    KJ Guest

    "Bar Nash" <> wrote in message
    news:gcsn28$qdb$...
    > Hi all
    >
    > How a FIR model is tested after verification and synthesys ?
    >


    The same way that anything else is tested. Generate stimulus and compare
    the actual output to predicted output.

    > I mean how do we know that the FIR will have the expected frequency
    > response when put on silicon ?
    >


    By generating stimulus over the entire expected input frequency range and,
    as stated above, comparing the actual output to the predicted output.

    Kevin Jennings
     
    KJ, Oct 12, 2008
    #2
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