fundamental question on process

[Praveen]

Hi all,

I have been looking at some code that raised a basic question. If we
have process like

process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;

when trigger is true are the 4 signal assignment statements executed
sequentially or concurrently ?

What happens when they are variable assignments like below

process
begin
wait on TRIGGER;
variable1 := Variable2;
Variable2 := Variable1 + Variable3;
Variable3 := signal2;
RESULT <= Variable1 + Variable2 + Variable3; -- RESULT is of
type signal
end process;


I tried simulating both of them and the results are different (because
of the variable/signal differnce on assignment).

The website where this example is cited
http://www.seas.upenn.edu/~ee201/vhdl/vhdl_primer.html#_Toc526061350
says ..when they are declared as variables they are executed
sequentially and when declared as signals are executed concurrently.
The book that I usually follow says (and I agree) that the signal
assignments are sequentially executed. Is'nt that the reason why
processes were created in the first place?

If they are executed sequentially, why do we get the different values
when they are declared as variables/signals.

Could someone help me out?

Thanks.

 

[jtw]

Hi all,

I have been looking at some code that raised a basic question. If we
have process like

process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;

when trigger is true are the 4 signal assignment statements executed
sequentially or concurrently ?
Concurrently.


What happens when they are variable assignments like below

process
begin
wait on TRIGGER;
variable1 := Variable2;
Variable2 := Variable1 + Variable3;
Variable3 := signal2;
RESULT <= Variable1 + Variable2 + Variable3; -- RESULT is of
type signal
end process;


I tried simulating both of them and the results are different (because
of the variable/signal differnce on assignment).

The website where this example is cited
http://www.seas.upenn.edu/~ee201/vhdl/vhdl_primer.html#_Toc526061350
says ..when they are declared as variables they are executed
sequentially and when declared as signals are executed concurrently.
The book that I usually follow says (and I agree) that the signal
assignments are sequentially executed. Is'nt that the reason why
processes were created in the first place?

Inside a process, the later assignments take precedence. E.g.,

process
begin
wait on clk='1';
dummy0 <= '1';
dummy0 <= not dummy0;
end process;

This toggles dummy0 (which yes, should be initialized somewhere.) Even
though the first dummy0 assignment is scheduled, it get's overwritten. The
last assignment takes precedence. For example, the following process
synchronously resets dummy0 when reset is '1', and synchronously sets dummy0
when reset is '0';

process
begin
wait on clk='1';
dummy0 <= '1';
if reset = '1' then
dummy0 <= '0';
end if;
end process;

 

[Egbert Molenkamp]

Hi all,

I have been looking at some code that raised a basic question. If we
have process like

process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;

when trigger is true are the 4 signal assignment statements executed
sequentially or concurrently ?

What happens when they are variable assignments like below

process
begin
wait on TRIGGER;
variable1 := Variable2;
Variable2 := Variable1 + Variable3;
Variable3 := signal2;
RESULT <= Variable1 + Variable2 + Variable3; -- RESULT is of
type signal
end process;


I tried simulating both of them and the results are different (because
of the variable/signal differnce on assignment).

The website where this example is cited
http://www.seas.upenn.edu/~ee201/vhdl/vhdl_primer.html#_Toc526061350
says ..when they are declared as variables they are executed
sequentially and when declared as signals are executed concurrently.
The book that I usually follow says (and I agree) that the signal
assignments are sequentially executed. Is'nt that the reason why
processes were created in the first place?

I copied a part of the document you refere to:
*************
It is important to understand the difference between variables and signals,
particularly how it relates to when their value changes. A variable changes
instantaneously when the variable assignment is executed. On the other hand,
a signal changes a delay after the assignment expression is evaluated. If no
delay is specified, the signal will change after a delta delay. This has
important consequences for the updated values of variables and signals. Lets
compare the two files in which a process is used to calculate the signal
RESULT [7].
*************

Notice that also the last line "has important consequences..".

The statement in both processes you give are exectured sequentially. However
in the first proces signal signal1 is not updated immediatly (it takes one
delta). Therefore the second sequential statement in that process "signal2
<= signal1 + signal3" uses the not updated value of signal1.
When is signal1 updated? When all concurrent statements have finished there
execution. Due to this mechanism concurrency is possible.

Egbert Molenkamp

 

[Praveen]

Thanks Wright and Egbert for the replies. I got the picture now.