How to implement the bus?

Discussion in 'VHDL' started by Vagant, Oct 9, 2007.

  1. Vagant

    Vagant Guest

    Hello All.

    I am a beginner in VHDL and want to ask how to implement a bus.
    The system which I want to design consists of host PC computer running
    Windows XP, a digital system which I want to design in ISE WebPack
    and implement on FPGA and a USB interface between the host and the
    system.
    The system consists of subcurcuits which have to communicate with host
    via USB interface as I have already said. My question is how to
    implement
    a bus which will connect the subcurcuits? What kind of bus it should
    be?
    Is a tristate bus a proper choice for this?

    Thank you.
    If my question is too general please give me some idea how it can be
    specialised.
    Vagant, Oct 9, 2007
    #1
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  2. Vagant schrieb:


    > My question is how to
    > implement
    > a bus which will connect the subcurcuits?


    > Is a tristate bus a proper choice for this?


    A tristate bus is an option, that works. The advantage is, that you can
    easily add components to the bus without changes in other components.
    The disadvantage is, that tristate drivers are not always available
    (especially not in all FPGAs) and if the bus becomes huge, which means
    the load of the bus becomes huge, then it may be that your target does
    not offer strong enough tristate drivers to drive the bus.

    Another option would be a classic multiplexer. This means every
    subcomponent drives its data output and a big multiplexer selects witch
    one is to be read. This solution is not too bad even if it sounds "huge".

    But I think a better solution is an OR- or AND-Bus. For an OR-Bus every
    subcomponent drives the selected value if it is selected or the data
    word zero if not. All outputs of all subcomponents then have to be ORed
    together. The AND bus is similar. Both OR and AND bus scale very well
    with the bus size (the synthesis tool can easily add buffers), are quite
    fast and dissipate less power than a tristate bus or a big classic
    multiplexer.

    Ralf
    Ralf Hildebrandt, Oct 9, 2007
    #2
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  3. Vagant wrote:

    > I am a beginner in VHDL and want to ask how to implement a bus.
    > The system which I want to design consists of host PC computer running
    > Windows XP, a digital system which I want to design in ISE WebPack
    > and implement on FPGA and a USB interface between the host and the
    > system.


    I would work out the USB interface details first.
    It could be an external chip, a purchased IP
    or your own vhdl code. This decision will affect
    your design entity interface. Connections
    between internal processes is a smaller problem.

    -- Mike Treseler
    Mike Treseler, Oct 9, 2007
    #3
  4. Vagant

    Vagant Guest

    On Oct 9, 5:52 pm, Mike Treseler <> wrote:
    > Vagant wrote:
    > > I am a beginner in VHDL and want to ask how to implement a bus.
    > > The system which I want to design consists of host PC computer running
    > > Windows XP, a digital system which I want to design in ISE WebPack
    > > and implement on FPGA and a USB interface between the host and the
    > > system.

    >
    > I would work out the USB interface details first.
    > It could be an external chip, a purchased IP
    > or your own vhdl code. This decision will affect
    > your design entity interface. Connections
    > between internal processes is a smaller problem.
    >
    > -- Mike Treseler


    Hi Mike,
    I am going to use USB module called UM245R from FTDI. There is a user
    mode driver (.dll) for this module and I believe that it makes working
    of USB just transparent - data just go forth and back through it
    without problems. Output
    of the UM245R module looks like a parallel port (8 bidirectional data
    lines).
    By the way, I wonder how such output can be connected to my system
    bus? As I know (from textbooks) there has to be adddress and command
    lines as well, not
    only data lines.
    Vagant, Oct 10, 2007
    #4
  5. Vagant

    Vagant Guest

    On Oct 9, 4:13 pm, Ralf Hildebrandt <> wrote:
    > Vagant schrieb:
    >
    > > My question is how to
    > > implement
    > > a bus which will connect the subcurcuits?
    > > Is a tristate bus a proper choice for this?

    >
    > A tristate bus is an option, that works. The advantage is, that you can
    > easily add components to the bus without changes in other components.
    > The disadvantage is, that tristate drivers are not always available
    > (especially not in all FPGAs) and if the bus becomes huge, which means
    > the load of the bus becomes huge, then it may be that your target does
    > not offer strong enough tristate drivers to drive the bus.
    >
    > Another option would be a classic multiplexer. This means every
    > subcomponent drives its data output and a big multiplexer selects witch
    > one is to be read. This solution is not too bad even if it sounds "huge".
    >
    > But I think a better solution is an OR- or AND-Bus. For an OR-Bus every
    > subcomponent drives the selected value if it is selected or the data
    > word zero if not. All outputs of all subcomponents then have to be ORed
    > together. The AND bus is similar. Both OR and AND bus scale very well
    > with the bus size (the synthesis tool can easily add buffers), are quite
    > fast and dissipate less power than a tristate bus or a big classic
    > multiplexer.
    >
    > Ralf


    Well, I never heard of OR- and AND- buses. I thought that only mux and
    tri-state buses exists. Thanks for this! I actually start thinking
    whether I should have bus at all. My system consists of pulse
    programmer, digital receiver, few filters - that's all and it is
    supposed to be controlled by host PC. Maybe it's better to connect all
    of them directly as required and do not implement bus at all. Though,
    in order to organise interface between host and system I have to use
    some sort of circuitry which allows bidirectional dataflow. Any
    suggestions, please!
    Vagant, Oct 10, 2007
    #5
  6. On Tue, 09 Oct 2007 07:59:19 -0700, Vagant
    <> wrote:

    >Hello All.
    >
    >I am a beginner in VHDL and want to ask how to implement a bus.
    >The system which I want to design consists of host PC computer running
    >Windows XP, a digital system which I want to design in ISE WebPack
    >and implement on FPGA and a USB interface between the host and the
    >system.
    >The system consists of subcurcuits which have to communicate with host
    >via USB interface as I have already said. My question is how to
    >implement
    >a bus which will connect the subcurcuits? What kind of bus it should
    >be?
    >Is a tristate bus a proper choice for this?


    It's probably the best choice between chips; e.g. your USB chip, the
    FPGA, and possibly also external memory. (That is, it's the most
    economical. But you can also keep connecting devices up to their own
    FPGA pins until you run out of pins).

    On-chip, between systems on the FPGA, other choices are better, such as
    the "Or" bus described elsewhere.

    An alternative, if you need to implement an embedded CPU on the FPGA,
    would be the CPU's own bus, e.g. OPB for Microblaze, or PLB for the
    Power PC in the Virtex-II Pro. These tend to be more complex, but have
    extensive tool support such as EDK (not free). IMO the complexity is not
    worthwhile unless you are using EDK or some such for system
    development.

    - Brian
    Brian Drummond, Oct 10, 2007
    #6
  7. Vagant wrote:

    > Hi Mike,
    > I am going to use USB module called UM245R from FTDI. There is a user
    > mode driver (.dll) for this module and I believe that it makes working
    > of USB just transparent - data just go forth and back through it
    > without problems. Output
    > of the UM245R module looks like a parallel port (8 bidirectional data
    > lines).


    Your fpga probably reads or writes or read data from a fifo.

    > By the way, I wonder how such output can be connected to my system
    > bus? As I know (from textbooks) there has to be adddress and command
    > lines as well, not
    > only data lines.



    Unless you have more than one USB port,
    this an external interface, not a bus.
    These are ports on your top design entity.

    See the data sheet or app notes for details.
    I would assume you would drive data to
    write to the interface and drive 'Z'
    to read using control bits from the chip
    and from the fpga to handshake somehow.

    Good luck.

    -- Mike Treseler
    Mike Treseler, Oct 10, 2007
    #7
  8. Vagant schrieb:

    > My system consists of pulse
    > programmer, digital receiver, few filters - that's all


    Don't think of specific components. It does not matter what are these
    components for. You just have some components, that have to be connected.


    > and it is
    > supposed to be controlled by host PC.


    That are two problems: (1) the connection of the internal components and
    (2) the connection between a component and a host PC.


    > Maybe it's better to connect all
    > of them directly as required and do not implement bus at all.


    No, because then you need dedicated communication capabilities (for
    communication to the host) for each component.

    Communication to a host is one problem and it is not too simple.


    > Though,
    > in order to organise interface between host and system I have to use
    > some sort of circuitry which allows bidirectional dataflow. Any
    > suggestions, please!


    RS232? USB?
    This strongly depends on the amount of data to be transferred and the
    available application at the host for data exchange. The host software
    is another bigger problem.

    The type of the internal bus is the most simple problem.

    Ralf
    Ralf Hildebrandt, Oct 15, 2007
    #8
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