How will synthesizers handle these statements?

Discussion in 'VHDL' started by Frank, Feb 2, 2006.

  1. Frank

    Frank Guest

    I put these conditions in different always and if-else-if statements, will
    design compiler & ISE be smart enough to recognise them and reduce
    hardware cost accordingly?

    I had a tendency to write the conditions with a wire & assign statement
    e.g.:
    wire cond1; assign cond1 = pop && (process == 8'h25) || kick;
    but if synthesizers handles these, then it will save me some thinking.






    always @ (posedge clk)
    begin
    if (pop && (process == 8'h25) || kick)
    whatever <= asdf;
    else if (pop1 && (process == 8'h25) || kick1)
    whatever <= asdf1;
    else if (pop2 && (process == 8'h25) || kick2)
    whatever <= asdf2;
    end

    always @ (posedge clk)
    begin
    if (pop && (process == 8'h25) || kick)
    whatever1 <= asdf3;
    else if (pop1 && (process == 8'h25) || kick1)
    whatever1 <= asdf4;
    else if (pop3 && (process == 8'h25) || kick3)
    whatever1 <= asdf5;
    end
    Frank, Feb 2, 2006
    #1
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  2. Frank

    Guest

    Try not to cross post. This isnt anything to do with VHDL
    , Feb 2, 2006
    #2
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  3. Frank

    Mahmoud Guest

    What about trying yourself?

    Frank wrote:
    > I put these conditions in different always and if-else-if statements, will
    > design compiler & ISE be smart enough to recognise them and reduce
    > hardware cost accordingly?
    >
    > I had a tendency to write the conditions with a wire & assign statement
    > e.g.:
    > wire cond1; assign cond1 = pop && (process == 8'h25) || kick;
    > but if synthesizers handles these, then it will save me some thinking.
    >
    >
    >
    >
    >
    >
    > always @ (posedge clk)
    > begin
    > if (pop && (process == 8'h25) || kick)
    > whatever <= asdf;
    > else if (pop1 && (process == 8'h25) || kick1)
    > whatever <= asdf1;
    > else if (pop2 && (process == 8'h25) || kick2)
    > whatever <= asdf2;
    > end
    >
    > always @ (posedge clk)
    > begin
    > if (pop && (process == 8'h25) || kick)
    > whatever1 <= asdf3;
    > else if (pop1 && (process == 8'h25) || kick1)
    > whatever1 <= asdf4;
    > else if (pop3 && (process == 8'h25) || kick3)
    > whatever1 <= asdf5;
    > end
    Mahmoud, Feb 2, 2006
    #3
  4. Frank

    Jason Zheng Guest

    Frank wrote:
    > I put these conditions in different always and if-else-if statements, will
    > design compiler & ISE be smart enough to recognise them and reduce
    > hardware cost accordingly?
    >

    There's an option in many synthesizers called "resource sharing" that
    will optimize for space if logic like these are found, but I think the
    default is to treat them as seperate blocks. Why bother with
    optimizations like this? IMO these should be the least to worry about.

    > but if synthesizers handles these, then it will save me some thinking.


    Do save yourself some thinking like this, let the synthesis tools worry
    about optimization.
    Jason Zheng, Feb 2, 2006
    #4
  5. Frank

    Guest

    In general, I don't think that a synthesis tool will share resources
    between always blocks.

    I find it best to "help" the synthesys tool where possible.

    I would re-write the above code (verilog is a bit rusty)

    parameter FinalCount := 8'h25 ;
    wire AtFinalCount <= (process == FinalCount) ? '1' : '0' ; // or
    always block

    always @(clk)
    begin
    if (pop0 && FinalCount) || kick0
    whatever <= asdf0 ;
    else if
    etc etc
    end // always
    , Feb 3, 2006
    #5
  6. Frank

    Rob Dekker Guest

    Hi Frank,

    The tests that you wrote will create what is called "common sub-expressions".
    These are typically eliminated very early in the flow through synthesis.

    So, I am convinced that you are free to write the same tests in different processes,
    and it should not affect the synthesis result.

    Just try to keep them the same as much as possible, so that common subexpression
    elimination is guaranteed to work.


    Rob



    "Frank" <> wrote in message news:43e176bb$...
    >I put these conditions in different always and if-else-if statements, will
    > design compiler & ISE be smart enough to recognise them and reduce
    > hardware cost accordingly?
    >
    > I had a tendency to write the conditions with a wire & assign statement
    > e.g.:
    > wire cond1; assign cond1 = pop && (process == 8'h25) || kick;
    > but if synthesizers handles these, then it will save me some thinking.
    >
    >
    >
    >
    >
    >
    > always @ (posedge clk)
    > begin
    > if (pop && (process == 8'h25) || kick)
    > whatever <= asdf;
    > else if (pop1 && (process == 8'h25) || kick1)
    > whatever <= asdf1;
    > else if (pop2 && (process == 8'h25) || kick2)
    > whatever <= asdf2;
    > end
    >
    > always @ (posedge clk)
    > begin
    > if (pop && (process == 8'h25) || kick)
    > whatever1 <= asdf3;
    > else if (pop1 && (process == 8'h25) || kick1)
    > whatever1 <= asdf4;
    > else if (pop3 && (process == 8'h25) || kick3)
    > whatever1 <= asdf5;
    > end
    >
    >
    >
    >
    Rob Dekker, Feb 3, 2006
    #6
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