No clock signals found in design...

Discussion in 'VHDL' started by Jerrie85, Aug 22, 2006.

  1. Jerrie85

    Jerrie85

    Joined:
    Aug 18, 2006
    Messages:
    7
    Whenever i synthesize i top level block in xilinx, i get this msg, "No clock signals found in design", so i dont get information about the clock speed or clock delay; this is wierd since i have a central clk signal that drives a lot of Flip flops

    how do i correct this in synthesis? how do i make xilinx realize i have a clk sig that needs to be treated appropriately? i have no IBUFs, or CLKBufs in design
    Jerrie85, Aug 22, 2006
    #1
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  2. Jerrie85

    Jerrie85

    Joined:
    Aug 18, 2006
    Messages:
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    i'm sure someone's got this before...does anyone know? pleasee help
    Jerrie85, Aug 24, 2006
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  3. Jerrie85

    Jerrie85

    Joined:
    Aug 18, 2006
    Messages:
    7
    i'm sure someone's got this before...does anyone know? pleasee help
    Jerrie85, Aug 24, 2006
    #3
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