Open Verification Libiary Free Download

Discussion in 'VHDL' started by Davy, Feb 8, 2006.

  1. Davy

    Davy Guest

    Hi all,

    I am a Verilog user and I want to find some tools do assertion(like C's
    assert()).

    I found Open Verification Libiary(OVL) has been updated. And it is free
    for download( http://www.accellera.org/activities/ovl/ ).

    I hope to use it in the near future.

    Anyone has used it yet? Please give some comment. Thanks!

    Best regards,
    Davy
     
    Davy, Feb 8, 2006
    #1
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  2. Davy

    Uncle Noah Guest

    not used it but does anybody know if it is going to be ported to VHDL
    too? (like the old OVLs)

    Regards
    Nikolaos Kavvadias
     
    Uncle Noah, Feb 8, 2006
    #2
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  3. Davy

    anupam Guest

    hi,
    Ya, i have used the OVLs for one of my projects
    Its good for verification if you have ample time ...
    You need to write all the possible assertions for a block and yet at
    later some point you will notice that there are some more to be written
    .......
    Try system Verilog assertions ,they are smart but a bit difficult to
    learn....

    regards,
    Anupam Jain
     
    anupam, Feb 9, 2006
    #3
  4. Davy

    anupam Guest

    Theres one library in VHDL too like in verilog ....


    regards,
    Anupam Jain
     
    anupam, Feb 9, 2006
    #4
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