Pin numbers assignment

[Merciadri Luca]

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Hi,

I'm using an entity `sorter', that I define using

==
entity sorter is
port(
CLK: in std_logic;
BTN_on: in std_logic;
LED_size: out std_logic;
);

attribute pin_numbers of sorter: entity is
"CLK:1 BTN_on:2 LED_size:14";

end sorter;
==

However, ispLEVER gives me `Reference to unknown attribute definition
pin_numbers'. What am I doing wrong?

Thanks.
- --
Merciadri Luca
See http://www.student.montefiore.ulg.ac.be/~merciadri/
- --

If you fake it, you can't make it.
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[StuartHobday]

Example of ispLever pin assigments:

ENTITY Demo IS
PORT ( Rst : IN std_logic;
Clk : IN std_logic
);

ATTRIBUTE LOC : string;
ATTRIBUTE LOC OF Rst : SIGNAL IS "112";
ATTRIBUTE LOC OF Clk : SIGNAL IS "124";

END Demo;

The pin syntax may vary between ispLever and ispLever CLASSIC, for example "112" maybe "P112"

 

[KJ]

On Nov 18, 7:03 am, Merciadri Luca <[email protected]>
wrote:

attribute pin_numbers of sorter: entity is
"CLK:1 BTN_on:2 LED_size:14";

However, ispLEVER gives me `Reference to unknown attribute definition
pin_numbers'. What am I doing wrong?

Before you can use an attribute, first you must define what that
attribute is in the first place. The attribute 'pin_numbers' is not a
pre-defined VHDL language attribute, it is a user defined
attribute...so you as the user need to define it. In your case, the
following statement is needed prior to your use of the attribute
statement that you have above.

attribute pin_numbers: STRING;

It is also likely that there is some Lattice specific library that has
this attribute definition included that you could get access to with a
'use' statement.

use work.xxx.all; -- Where xxx is the name of the Lattice lib

Lastly, although you may have no intention of ever porting your design
to any other device, it is generally not a good idea to embed pin
definitions in the source code. If you DO end up moving to a
different device (maybe from QFP to BGA as an example, or a bigger
part) then those pin definitions in the source code are useless...and
in the way now because they are in the source code. Using attributes
is also tool dependent (if you move the code from say Lattice to
Altera, Xilinx, etc.) and the tools that you use will usually give you
an easier way to enter the pin info. Since you will need to archive
the synthesis tool files anyway there is no reason that the pin number
information can't be kept there also. You will likely have other
constraints archived there such as timing constraints so there is no
reason why pin number constraints can't be there also.

Think of it this way, the VHDL you write is intended to define a logic
description. A logic description does not inherently require any
specific technology implementation. So any design constraints that
are dependent on the underlying technology should generally be stored
with whatever tool it is that allows one to implement the logic
description in that technology. Use that as your criteria for
deciding whether or not to define a constraint in the VHDL source code
or elsewhere.

Kevin Jennings

 

[dgreig]

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Hi,

I'm using an entity `sorter', that I define using

==
entity sorter is
port(
        CLK: in std_logic;
        BTN_on: in std_logic;
        LED_size: out std_logic;
);

attribute pin_numbers of sorter: entity is
"CLK:1 BTN_on:2 LED_size:14";

end sorter;
==

However, ispLEVER gives me `Reference to unknown attribute definition
pin_numbers'. What am I doing wrong?

Thanks.
- --
Merciadri Luca
Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/
- --

If you fake it, you can't make it.
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Try the predefined '93 "chip_pin".
The synthesis tool may or may not support it however.

I hate to admit knowing this one..

DG

 

[Merciadri Luca]

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On Nov 18, 7:03 am, Merciadri Luca <[email protected]>
wrote:



Before you can use an attribute, first you must define what that
attribute is in the first place. The attribute 'pin_numbers' is not a
pre-defined VHDL language attribute, it is a user defined
attribute...so you as the user need to define it. In your case, the
following statement is needed prior to your use of the attribute
statement that you have above.

attribute pin_numbers: STRING;

It is also likely that there is some Lattice specific library that has
this attribute definition included that you could get access to with a
'use' statement.

use work.xxx.all; -- Where xxx is the name of the Lattice lib

Lastly, although you may have no intention of ever porting your design
to any other device, it is generally not a good idea to embed pin
definitions in the source code. If you DO end up moving to a
different device (maybe from QFP to BGA as an example, or a bigger
part) then those pin definitions in the source code are useless...and
in the way now because they are in the source code. Using attributes
is also tool dependent (if you move the code from say Lattice to
Altera, Xilinx, etc.) and the tools that you use will usually give you
an easier way to enter the pin info. Since you will need to archive
the synthesis tool files anyway there is no reason that the pin number
information can't be kept there also. You will likely have other
constraints archived there such as timing constraints so there is no
reason why pin number constraints can't be there also.

Think of it this way, the VHDL you write is intended to define a logic
description. A logic description does not inherently require any
specific technology implementation. So any design constraints that
are dependent on the underlying technology should generally be stored
with whatever tool it is that allows one to implement the logic
description in that technology. Use that as your criteria for
deciding whether or not to define a constraint in the VHDL source code
or elsewhere.

Thanks for your answers.

- --
Merciadri Luca
See http://www.student.montefiore.ulg.ac.be/~merciadri/
- --

Give a man a fish and you feed him for a day; teach a man to fish
and you feed him for a lifetime.
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